bebbc4bcf3
Add module parameter xilinx_uartps.rx_trigger_level=32 to command line options for CSP to set Rx watermark for xuartps driver lower than the default value, to avoid UART overruns at 115200 bps. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
55 lines
1 KiB
Plaintext
55 lines
1 KiB
Plaintext
/dts-v1/;
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/ {
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compatible = "cdns,xtensa-xtfpga";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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chosen {
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bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x40000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "cdns,xtensa-cpu";
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reg = <0>;
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};
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};
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pic: pic {
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compatible = "cdns,xtensa-pic";
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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clocks {
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osc: main-oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x00000000 0xf0000000 0x10000000>;
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uart0: serial@0d000000 {
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compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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clocks = <&osc>, <&osc>;
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clock-names = "uart_clk", "pclk";
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reg = <0x0d000000 0x1000>;
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interrupts = <0 1>;
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};
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};
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};
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