09230cbc1b
This way we have one central definition of it, and user can select it as needed. The new option is not user visible, which is the behavior it had in most architectures, with a few notable exceptions: - On x86_64 and mips/loongson3 it used to be user selectable, but defaulted to y. It now is unconditional, which seems like the right thing for 64-bit architectures without guaranteed availablity of IOMMUs. - on powerpc the symbol is user selectable and defaults to n, but many boards select it. This change assumes no working setup required a manual selection, but if that turned out to be wrong we'll have to add another select statement or two for the respective boards. Signed-off-by: Christoph Hellwig <hch@lst.de>
42 lines
1.1 KiB
Plaintext
42 lines
1.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
|
|
comment "Processor Type"
|
|
|
|
# Select CPU types depending on the architecture selected. This selects
|
|
# which CPUs we support in the kernel image, and the compiler instruction
|
|
# optimiser behaviour.
|
|
|
|
config CPU_UCV2
|
|
def_bool y
|
|
|
|
comment "Processor Features"
|
|
|
|
config CPU_ICACHE_DISABLE
|
|
bool "Disable I-Cache (I-bit)"
|
|
help
|
|
Say Y here to disable the processor instruction cache. Unless
|
|
you have a reason not to or are unsure, say N.
|
|
|
|
config CPU_DCACHE_DISABLE
|
|
bool "Disable D-Cache (D-bit)"
|
|
help
|
|
Say Y here to disable the processor data cache. Unless
|
|
you have a reason not to or are unsure, say N.
|
|
|
|
config CPU_DCACHE_WRITETHROUGH
|
|
bool "Force write through D-cache"
|
|
help
|
|
Say Y here to use the data cache in writethrough mode. Unless you
|
|
specifically require this or are unsure, say N.
|
|
|
|
config CPU_DCACHE_LINE_DISABLE
|
|
bool "Disable D-cache line ops"
|
|
default y
|
|
help
|
|
Say Y here to disable the data cache line operations.
|
|
|
|
config CPU_TLB_SINGLE_ENTRY_DISABLE
|
|
bool "Disable TLB single entry ops"
|
|
default y
|
|
help
|
|
Say Y here to disable the TLB single entry operations.
|