4e0ae876f7
AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
14 lines
308 B
C
14 lines
308 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for AM654 SERDES.
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*/
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#ifndef _DT_BINDINGS_AM654_SERDES
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#define _DT_BINDINGS_AM654_SERDES
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#define AM654_SERDES_CMU_REFCLK 0
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#define AM654_SERDES_LO_REFCLK 1
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#define AM654_SERDES_RO_REFCLK 2
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#endif /* _DT_BINDINGS_AM654_SERDES */
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