9952f6918d
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
43 lines
938 B
C
43 lines
938 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef DT_RESET_OXSEMI_OX820_H
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#define DT_RESET_OXSEMI_OX820_H
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#define RESET_SCU 0
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#define RESET_LEON 1
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#define RESET_ARM0 2
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#define RESET_ARM1 3
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#define RESET_USBHS 4
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#define RESET_USBPHYA 5
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#define RESET_MAC 6
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#define RESET_PCIEA 7
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#define RESET_SGDMA 8
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#define RESET_CIPHER 9
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#define RESET_DDR 10
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#define RESET_SATA 11
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#define RESET_SATA_LINK 12
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#define RESET_SATA_PHY 13
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#define RESET_PCIEPHY 14
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#define RESET_NAND 15
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#define RESET_GPIO 16
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#define RESET_UART1 17
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#define RESET_UART2 18
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#define RESET_MISC 19
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#define RESET_I2S 20
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#define RESET_SD 21
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#define RESET_MAC_2 22
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#define RESET_PCIEB 23
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#define RESET_VIDEO 24
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#define RESET_DDR_PHY 25
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#define RESET_USBPHYB 26
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#define RESET_USBDEV 27
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/* Reserved 29 */
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#define RESET_ARMDBG 29
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#define RESET_PLLA 30
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#define RESET_PLLB 31
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#endif /* DT_RESET_OXSEMI_OX820_H */
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