![Kumar Gala](/assets/img/avatar_default.png)
Added a proper prototype for cpm2_reset() which gets rid of a build warning. Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
198 lines
4.9 KiB
C
198 lines
4.9 KiB
C
/*
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* General Purpose functions for the global management of the
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* 8260 Communication Processor Module.
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* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
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* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
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* 2.3.99 Updates
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mpc8260.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/cpm2.h>
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#include <asm/rheap.h>
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static void cpm2_dpinit(void);
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cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
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/* We allocate this here because it is used almost exclusively for
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* the communication processor devices.
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*/
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cpm2_map_t *cpm2_immr;
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#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
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of space for CPM as it is larger
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than on PQ2 */
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void
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cpm2_reset(void)
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{
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cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
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/* Reclaim the DP memory for our use.
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*/
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cpm2_dpinit();
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/* Tell everyone where the comm processor resides.
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*/
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cpmp = &cpm2_immr->im_cpm;
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}
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/* Set a baud rate generator. This needs lots of work. There are
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* eight BRGs, which can be connected to the CPM channels or output
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* as clocks. The BRGs are in two different block of internal
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* memory mapped space.
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* The baud rate clock is the system clock divided by something.
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* It was set up long ago during the initial boot phase and is
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* is given to us.
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* Baud rate clocks are zero-based in the driver code (as that maps
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* to port numbers). Documentation uses 1-based numbering.
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*/
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#define BRG_INT_CLK (((bd_t *)__res)->bi_brgfreq)
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#define BRG_UART_CLK (BRG_INT_CLK/16)
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/* This function is used by UARTS, or anything else that uses a 16x
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* oversampled clock.
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*/
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void
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cpm_setbrg(uint brg, uint rate)
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{
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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if (brg < 4) {
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bp = (uint *)&cpm2_immr->im_brgc1;
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}
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else {
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bp = (uint *)&cpm2_immr->im_brgc5;
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brg -= 4;
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}
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bp += brg;
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*bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN;
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}
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/* This function is used to set high speed synchronous baud rate
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* clocks.
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*/
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void
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cpm2_fastbrg(uint brg, uint rate, int div16)
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{
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volatile uint *bp;
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if (brg < 4) {
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bp = (uint *)&cpm2_immr->im_brgc1;
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}
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else {
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bp = (uint *)&cpm2_immr->im_brgc5;
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brg -= 4;
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}
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bp += brg;
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*bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
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if (div16)
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*bp |= CPM_BRG_DIV16;
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}
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/*
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* dpalloc / dpfree bits.
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*/
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static spinlock_t cpm_dpmem_lock;
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/* 16 blocks should be enough to satisfy all requests
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* until the memory subsystem goes up... */
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static rh_block_t cpm_boot_dpmem_rh_block[16];
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static rh_info_t cpm_dpmem_info;
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static void cpm2_dpinit(void)
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{
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spin_lock_init(&cpm_dpmem_lock);
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/* initialize the info header */
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rh_init(&cpm_dpmem_info, 1,
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sizeof(cpm_boot_dpmem_rh_block) /
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sizeof(cpm_boot_dpmem_rh_block[0]),
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cpm_boot_dpmem_rh_block);
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/* Attach the usable dpmem area */
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/* XXX: This is actually crap. CPM_DATAONLY_BASE and
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* CPM_DATAONLY_SIZE is only a subset of the available dpram. It
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* varies with the processor and the microcode patches activated.
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* But the following should be at least safe.
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*/
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rh_attach_region(&cpm_dpmem_info, (void *)CPM_DATAONLY_BASE,
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CPM_DATAONLY_SIZE);
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}
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/* This function returns an index into the DPRAM area.
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*/
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uint cpm_dpalloc(uint size, uint align)
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{
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void *start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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cpm_dpmem_info.alignment = align;
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start = rh_alloc(&cpm_dpmem_info, size, "commproc");
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return (uint)start;
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}
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EXPORT_SYMBOL(cpm_dpalloc);
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int cpm_dpfree(uint offset)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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ret = rh_free(&cpm_dpmem_info, (void *)offset);
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(cpm_dpfree);
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/* not sure if this is ever needed */
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uint cpm_dpalloc_fixed(uint offset, uint size, uint align)
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{
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void *start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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cpm_dpmem_info.alignment = align;
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start = rh_alloc_fixed(&cpm_dpmem_info, (void *)offset, size, "commproc");
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return (uint)start;
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}
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EXPORT_SYMBOL(cpm_dpalloc_fixed);
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void cpm_dpdump(void)
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{
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rh_dump(&cpm_dpmem_info);
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}
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EXPORT_SYMBOL(cpm_dpdump);
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void *cpm_dpram_addr(uint offset)
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{
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return (void *)&cpm2_immr->im_dprambase[offset];
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}
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EXPORT_SYMBOL(cpm_dpram_addr);
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