![Thomas Gleixner](/assets/img/avatar_default.png)
Convert the initializers of hw_interrupt_type structures to C99 initializers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
209 lines
4.9 KiB
C
209 lines
4.9 KiB
C
#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/i8259.h>
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static volatile unsigned char *pci_intack; /* RO, gives us the irq vector */
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unsigned char cached_8259[2] = { 0xff, 0xff };
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#define cached_A1 (cached_8259[0])
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#define cached_21 (cached_8259[1])
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static DEFINE_SPINLOCK(i8259_lock);
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int i8259_pic_irq_offset;
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/*
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* Acknowledge the IRQ using either the PCI host bridge's interrupt
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* acknowledge feature or poll. How i8259_init() is called determines
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* which is called. It should be noted that polling is broken on some
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* IBM and Motorola PReP boxes so we must use the int-ack feature on them.
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*/
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int
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i8259_irq(struct pt_regs *regs)
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{
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int irq;
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spin_lock(&i8259_lock);
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/* Either int-ack or poll for the IRQ */
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if (pci_intack)
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irq = *pci_intack;
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else {
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/* Perform an interrupt acknowledge cycle on controller 1. */
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outb(0x0C, 0x20); /* prepare for poll */
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irq = inb(0x20) & 7;
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if (irq == 2 ) {
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/*
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* Interrupt is cascaded so perform interrupt
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* acknowledge on controller 2.
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*/
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outb(0x0C, 0xA0); /* prepare for poll */
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irq = (inb(0xA0) & 7) + 8;
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}
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}
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if (irq == 7) {
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/*
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* This may be a spurious interrupt.
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*
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* Read the interrupt status register (ISR). If the most
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* significant bit is not set then there is no valid
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* interrupt.
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*/
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if (!pci_intack)
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outb(0x0B, 0x20); /* ISR register */
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if(~inb(0x20) & 0x80)
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irq = -1;
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}
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spin_unlock(&i8259_lock);
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return irq;
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}
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static void i8259_mask_and_ack_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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if ( irq_nr >= i8259_pic_irq_offset )
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irq_nr -= i8259_pic_irq_offset;
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if (irq_nr > 7) {
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cached_A1 |= 1 << (irq_nr-8);
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inb(0xA1); /* DUMMY */
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outb(cached_A1,0xA1);
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outb(0x20,0xA0); /* Non-specific EOI */
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outb(0x20,0x20); /* Non-specific EOI to cascade */
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} else {
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cached_21 |= 1 << irq_nr;
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inb(0x21); /* DUMMY */
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outb(cached_21,0x21);
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outb(0x20,0x20); /* Non-specific EOI */
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}
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static void i8259_set_irq_mask(int irq_nr)
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{
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outb(cached_A1,0xA1);
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outb(cached_21,0x21);
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}
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static void i8259_mask_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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if ( irq_nr >= i8259_pic_irq_offset )
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irq_nr -= i8259_pic_irq_offset;
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if ( irq_nr < 8 )
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cached_21 |= 1 << irq_nr;
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else
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cached_A1 |= 1 << (irq_nr-8);
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i8259_set_irq_mask(irq_nr);
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static void i8259_unmask_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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if ( irq_nr >= i8259_pic_irq_offset )
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irq_nr -= i8259_pic_irq_offset;
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if ( irq_nr < 8 )
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cached_21 &= ~(1 << irq_nr);
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else
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cached_A1 &= ~(1 << (irq_nr-8));
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i8259_set_irq_mask(irq_nr);
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spin_unlock_irqrestore(&i8259_lock, flags);
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}
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static void i8259_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq].action)
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i8259_unmask_irq(irq);
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}
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struct hw_interrupt_type i8259_pic = {
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.typename = " i8259 ",
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.enable = i8259_unmask_irq,
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.disable = i8259_mask_irq,
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.ack = i8259_mask_and_ack_irq,
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.end = i8259_end_irq,
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};
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static struct resource pic1_iores = {
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.name = "8259 (master)",
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.start = 0x20,
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.end = 0x21,
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.flags = IORESOURCE_BUSY,
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};
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static struct resource pic2_iores = {
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.name = "8259 (slave)",
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.start = 0xa0,
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.end = 0xa1,
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.flags = IORESOURCE_BUSY,
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};
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static struct resource pic_edgectrl_iores = {
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.name = "8259 edge control",
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.start = 0x4d0,
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.end = 0x4d1,
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.flags = IORESOURCE_BUSY,
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};
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static struct irqaction i8259_irqaction = {
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.handler = no_action,
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.flags = SA_INTERRUPT,
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.mask = CPU_MASK_NONE,
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.name = "82c59 secondary cascade",
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};
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/*
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* i8259_init()
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* intack_addr - PCI interrupt acknowledge (real) address which will return
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* the active irq from the 8259
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*/
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void __init
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i8259_init(long intack_addr)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259_lock, flags);
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/* init master interrupt controller */
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outb(0x11, 0x20); /* Start init sequence */
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outb(0x00, 0x21); /* Vector base */
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outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
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outb(0x01, 0x21); /* Select 8086 mode */
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/* init slave interrupt controller */
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outb(0x11, 0xA0); /* Start init sequence */
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outb(0x08, 0xA1); /* Vector base */
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outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
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outb(0x01, 0xA1); /* Select 8086 mode */
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/* always read ISR */
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outb(0x0B, 0x20);
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outb(0x0B, 0xA0);
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/* Mask all interrupts */
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outb(cached_A1, 0xA1);
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outb(cached_21, 0x21);
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spin_unlock_irqrestore(&i8259_lock, flags);
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/* reserve our resources */
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setup_irq( i8259_pic_irq_offset + 2, &i8259_irqaction);
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request_resource(&ioport_resource, &pic1_iores);
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request_resource(&ioport_resource, &pic2_iores);
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request_resource(&ioport_resource, &pic_edgectrl_iores);
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if (intack_addr != 0)
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pci_intack = ioremap(intack_addr, 1);
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}
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