![Vitaly Bordug](/assets/img/avatar_default.png)
This patch adds on-chip PCI bridge support for the PQ2 family. The incomplete existent code is updated with interrupt handling stuff and board-specific bits for 8272ADS and PQ2FADS; the related files were renamed (from m8260_pci to m82xx_pci) to be of more generic fashion. This is tested with 8266ADS and 8272ADS, should work on PQ2FADS as well. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
474 lines
13 KiB
C
474 lines
13 KiB
C
/*
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* arch/ppc/platforms/mpc8260_pci9.c
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*
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* Workaround for device erratum PCI 9.
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* See Motorola's "XPC826xA Family Device Errata Reference."
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* The erratum applies to all 8260 family Hip4 processors. It is scheduled
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* to be fixed in HiP4 Rev C. Erratum PCI 9 states that a simultaneous PCI
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* inbound write transaction and PCI outbound read transaction can result in a
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* bus deadlock. The suggested workaround is to use the IDMA controller to
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* perform all reads from PCI configuration, memory, and I/O space.
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*
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* Author: andy_lowe@mvista.com
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*
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* 2003 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <asm/io.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/byteorder.h>
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#include <asm/mpc8260.h>
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#include <asm/immap_cpm2.h>
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#include <asm/cpm2.h>
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#include "m82xx_pci.h"
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#ifdef CONFIG_8260_PCI9
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/*#include <asm/mpc8260_pci9.h>*/ /* included in asm/io.h */
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#define IDMA_XFER_BUF_SIZE 64 /* size of the IDMA transfer buffer */
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/* define a structure for the IDMA dpram usage */
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typedef struct idma_dpram_s {
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idma_t pram; /* IDMA parameter RAM */
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u_char xfer_buf[IDMA_XFER_BUF_SIZE]; /* IDMA transfer buffer */
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idma_bd_t bd; /* buffer descriptor */
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} idma_dpram_t;
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/* define offsets relative to start of IDMA dpram */
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#define IDMA_XFER_BUF_OFFSET (sizeof(idma_t))
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#define IDMA_BD_OFFSET (sizeof(idma_t) + IDMA_XFER_BUF_SIZE)
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/* define globals */
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static volatile idma_dpram_t *idma_dpram;
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/* Exactly one of CONFIG_8260_PCI9_IDMAn must be defined,
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* where n is 1, 2, 3, or 4. This selects the IDMA channel used for
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* the PCI9 workaround.
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*/
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#ifdef CONFIG_8260_PCI9_IDMA1
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#define IDMA_CHAN 0
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#define PROFF_IDMA PROFF_IDMA1_BASE
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#define IDMA_PAGE CPM_CR_IDMA1_PAGE
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#define IDMA_SBLOCK CPM_CR_IDMA1_SBLOCK
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#endif
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#ifdef CONFIG_8260_PCI9_IDMA2
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#define IDMA_CHAN 1
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#define PROFF_IDMA PROFF_IDMA2_BASE
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#define IDMA_PAGE CPM_CR_IDMA2_PAGE
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#define IDMA_SBLOCK CPM_CR_IDMA2_SBLOCK
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#endif
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#ifdef CONFIG_8260_PCI9_IDMA3
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#define IDMA_CHAN 2
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#define PROFF_IDMA PROFF_IDMA3_BASE
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#define IDMA_PAGE CPM_CR_IDMA3_PAGE
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#define IDMA_SBLOCK CPM_CR_IDMA3_SBLOCK
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#endif
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#ifdef CONFIG_8260_PCI9_IDMA4
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#define IDMA_CHAN 3
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#define PROFF_IDMA PROFF_IDMA4_BASE
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#define IDMA_PAGE CPM_CR_IDMA4_PAGE
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#define IDMA_SBLOCK CPM_CR_IDMA4_SBLOCK
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#endif
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void idma_pci9_init(void)
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{
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uint dpram_offset;
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volatile idma_t *pram;
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volatile im_idma_t *idma_reg;
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volatile cpm2_map_t *immap = cpm2_immr;
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/* allocate IDMA dpram */
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dpram_offset = cpm_dpalloc(sizeof(idma_dpram_t), 64);
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idma_dpram = cpm_dpram_addr(dpram_offset);
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/* initialize the IDMA parameter RAM */
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memset((void *)idma_dpram, 0, sizeof(idma_dpram_t));
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pram = &idma_dpram->pram;
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pram->ibase = dpram_offset + IDMA_BD_OFFSET;
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pram->dpr_buf = dpram_offset + IDMA_XFER_BUF_OFFSET;
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pram->ss_max = 32;
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pram->dts = 32;
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/* initialize the IDMA_BASE pointer to the IDMA parameter RAM */
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*((ushort *) &immap->im_dprambase[PROFF_IDMA]) = dpram_offset;
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/* initialize the IDMA registers */
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idma_reg = (volatile im_idma_t *) &immap->im_sdma.sdma_idsr1;
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idma_reg[IDMA_CHAN].idmr = 0; /* mask all IDMA interrupts */
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idma_reg[IDMA_CHAN].idsr = 0xff; /* clear all event flags */
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printk("<4>Using IDMA%d for MPC8260 device erratum PCI 9 workaround\n",
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IDMA_CHAN + 1);
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return;
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}
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/* Use the IDMA controller to transfer data from I/O memory to local RAM.
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* The src address must be a physical address suitable for use by the DMA
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* controller with no translation. The dst address must be a kernel virtual
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* address. The dst address is translated to a physical address via
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* virt_to_phys().
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* The sinc argument specifies whether or not the source address is incremented
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* by the DMA controller. The source address is incremented if and only if sinc
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* is non-zero. The destination address is always incremented since the
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* destination is always host RAM.
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*/
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static void
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idma_pci9_read(u8 *dst, u8 *src, int bytes, int unit_size, int sinc)
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{
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unsigned long flags;
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volatile idma_t *pram = &idma_dpram->pram;
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volatile idma_bd_t *bd = &idma_dpram->bd;
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volatile cpm2_map_t *immap = cpm2_immr;
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local_irq_save(flags);
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/* initialize IDMA parameter RAM for this transfer */
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if (sinc)
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pram->dcm = IDMA_DCM_DMA_WRAP_64 | IDMA_DCM_SINC
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| IDMA_DCM_DINC | IDMA_DCM_SD_MEM2MEM;
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else
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pram->dcm = IDMA_DCM_DMA_WRAP_64 | IDMA_DCM_DINC
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| IDMA_DCM_SD_MEM2MEM;
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pram->ibdptr = pram->ibase;
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pram->sts = unit_size;
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pram->istate = 0;
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/* initialize the buffer descriptor */
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bd->dst = virt_to_phys(dst);
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bd->src = (uint) src;
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bd->len = bytes;
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bd->flags = IDMA_BD_V | IDMA_BD_W | IDMA_BD_I | IDMA_BD_L | IDMA_BD_DGBL
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| IDMA_BD_DBO_BE | IDMA_BD_SBO_BE | IDMA_BD_SDTB;
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/* issue the START_IDMA command to the CP */
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while (immap->im_cpm.cp_cpcr & CPM_CR_FLG);
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immap->im_cpm.cp_cpcr = mk_cr_cmd(IDMA_PAGE, IDMA_SBLOCK, 0,
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CPM_CR_START_IDMA) | CPM_CR_FLG;
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while (immap->im_cpm.cp_cpcr & CPM_CR_FLG);
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/* wait for transfer to complete */
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while(bd->flags & IDMA_BD_V);
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local_irq_restore(flags);
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return;
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}
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/* Use the IDMA controller to transfer data from I/O memory to local RAM.
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* The dst address must be a physical address suitable for use by the DMA
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* controller with no translation. The src address must be a kernel virtual
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* address. The src address is translated to a physical address via
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* virt_to_phys().
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* The dinc argument specifies whether or not the dest address is incremented
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* by the DMA controller. The source address is incremented if and only if sinc
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* is non-zero. The source address is always incremented since the
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* source is always host RAM.
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*/
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static void
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idma_pci9_write(u8 *dst, u8 *src, int bytes, int unit_size, int dinc)
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{
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unsigned long flags;
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volatile idma_t *pram = &idma_dpram->pram;
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volatile idma_bd_t *bd = &idma_dpram->bd;
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volatile cpm2_map_t *immap = cpm2_immr;
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local_irq_save(flags);
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/* initialize IDMA parameter RAM for this transfer */
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if (dinc)
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pram->dcm = IDMA_DCM_DMA_WRAP_64 | IDMA_DCM_SINC
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| IDMA_DCM_DINC | IDMA_DCM_SD_MEM2MEM;
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else
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pram->dcm = IDMA_DCM_DMA_WRAP_64 | IDMA_DCM_SINC
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| IDMA_DCM_SD_MEM2MEM;
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pram->ibdptr = pram->ibase;
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pram->sts = unit_size;
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pram->istate = 0;
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/* initialize the buffer descriptor */
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bd->dst = (uint) dst;
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bd->src = virt_to_phys(src);
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bd->len = bytes;
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bd->flags = IDMA_BD_V | IDMA_BD_W | IDMA_BD_I | IDMA_BD_L | IDMA_BD_DGBL
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| IDMA_BD_DBO_BE | IDMA_BD_SBO_BE | IDMA_BD_SDTB;
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/* issue the START_IDMA command to the CP */
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while (immap->im_cpm.cp_cpcr & CPM_CR_FLG);
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immap->im_cpm.cp_cpcr = mk_cr_cmd(IDMA_PAGE, IDMA_SBLOCK, 0,
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CPM_CR_START_IDMA) | CPM_CR_FLG;
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while (immap->im_cpm.cp_cpcr & CPM_CR_FLG);
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/* wait for transfer to complete */
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while(bd->flags & IDMA_BD_V);
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local_irq_restore(flags);
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return;
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}
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/* Same as idma_pci9_read, but 16-bit little-endian byte swapping is performed
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* if the unit_size is 2, and 32-bit little-endian byte swapping is performed if
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* the unit_size is 4.
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*/
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static void
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idma_pci9_read_le(u8 *dst, u8 *src, int bytes, int unit_size, int sinc)
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{
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int i;
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u8 *p;
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idma_pci9_read(dst, src, bytes, unit_size, sinc);
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switch(unit_size) {
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case 2:
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for (i = 0, p = dst; i < bytes; i += 2, p += 2)
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swab16s((u16 *) p);
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break;
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case 4:
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for (i = 0, p = dst; i < bytes; i += 4, p += 4)
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swab32s((u32 *) p);
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break;
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default:
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break;
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}
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}
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EXPORT_SYMBOL(idma_pci9_init);
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EXPORT_SYMBOL(idma_pci9_read);
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EXPORT_SYMBOL(idma_pci9_read_le);
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static inline int is_pci_mem(unsigned long addr)
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{
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if (addr >= M82xx_PCI_LOWER_MMIO &&
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addr <= M82xx_PCI_UPPER_MMIO)
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return 1;
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if (addr >= M82xx_PCI_LOWER_MEM &&
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addr <= M82xx_PCI_UPPER_MEM)
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return 1;
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return 0;
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}
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#define is_pci_mem(pa) ( (pa > 0x80000000) && (pa < 0xc0000000))
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int readb(volatile unsigned char *addr)
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{
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u8 val;
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unsigned long pa = iopa((unsigned long) addr);
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if (!is_pci_mem(pa))
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return in_8(addr);
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idma_pci9_read((u8 *)&val, (u8 *)pa, sizeof(val), sizeof(val), 0);
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return val;
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}
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int readw(volatile unsigned short *addr)
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{
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u16 val;
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unsigned long pa = iopa((unsigned long) addr);
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if (!is_pci_mem(pa))
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return in_le16(addr);
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idma_pci9_read((u8 *)&val, (u8 *)pa, sizeof(val), sizeof(val), 0);
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return swab16(val);
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}
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unsigned readl(volatile unsigned *addr)
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{
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u32 val;
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unsigned long pa = iopa((unsigned long) addr);
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if (!is_pci_mem(pa))
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return in_le32(addr);
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idma_pci9_read((u8 *)&val, (u8 *)pa, sizeof(val), sizeof(val), 0);
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return swab32(val);
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}
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int inb(unsigned port)
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{
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u8 val;
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u8 *addr = (u8 *)(port + _IO_BASE);
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idma_pci9_read((u8 *)&val, (u8 *)addr, sizeof(val), sizeof(val), 0);
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return val;
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}
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int inw(unsigned port)
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{
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u16 val;
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u8 *addr = (u8 *)(port + _IO_BASE);
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idma_pci9_read((u8 *)&val, (u8 *)addr, sizeof(val), sizeof(val), 0);
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return swab16(val);
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}
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unsigned inl(unsigned port)
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{
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u32 val;
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u8 *addr = (u8 *)(port + _IO_BASE);
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idma_pci9_read((u8 *)&val, (u8 *)addr, sizeof(val), sizeof(val), 0);
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return swab32(val);
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}
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void insb(unsigned port, void *buf, int ns)
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{
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u8 *addr = (u8 *)(port + _IO_BASE);
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idma_pci9_read((u8 *)buf, (u8 *)addr, ns*sizeof(u8), sizeof(u8), 0);
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}
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void insw(unsigned port, void *buf, int ns)
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{
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u8 *addr = (u8 *)(port + _IO_BASE);
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idma_pci9_read((u8 *)buf, (u8 *)addr, ns*sizeof(u16), sizeof(u16), 0);
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}
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void insl(unsigned port, void *buf, int nl)
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{
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u8 *addr = (u8 *)(port + _IO_BASE);
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idma_pci9_read((u8 *)buf, (u8 *)addr, nl*sizeof(u32), sizeof(u32), 0);
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}
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void insw_ns(unsigned port, void *buf, int ns)
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{
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u8 *addr = (u8 *)(port + _IO_BASE);
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idma_pci9_read((u8 *)buf, (u8 *)addr, ns*sizeof(u16), sizeof(u16), 0);
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}
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void insl_ns(unsigned port, void *buf, int nl)
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{
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u8 *addr = (u8 *)(port + _IO_BASE);
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idma_pci9_read((u8 *)buf, (u8 *)addr, nl*sizeof(u32), sizeof(u32), 0);
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}
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void *memcpy_fromio(void *dest, unsigned long src, size_t count)
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{
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unsigned long pa = iopa((unsigned long) src);
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if (is_pci_mem(pa))
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idma_pci9_read((u8 *)dest, (u8 *)pa, count, 32, 1);
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else
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memcpy(dest, (void *)src, count);
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return dest;
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}
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EXPORT_SYMBOL(readb);
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EXPORT_SYMBOL(readw);
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EXPORT_SYMBOL(readl);
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EXPORT_SYMBOL(inb);
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EXPORT_SYMBOL(inw);
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EXPORT_SYMBOL(inl);
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EXPORT_SYMBOL(insb);
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EXPORT_SYMBOL(insw);
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EXPORT_SYMBOL(insl);
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EXPORT_SYMBOL(insw_ns);
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EXPORT_SYMBOL(insl_ns);
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EXPORT_SYMBOL(memcpy_fromio);
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#endif /* ifdef CONFIG_8260_PCI9 */
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/* Indirect PCI routines adapted from arch/ppc/kernel/indirect_pci.c.
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* Copyright (C) 1998 Gabriel Paubert.
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*/
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#ifndef CONFIG_8260_PCI9
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#define cfg_read(val, addr, type, op) *val = op((type)(addr))
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#else
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#define cfg_read(val, addr, type, op) \
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idma_pci9_read_le((u8*)(val),(u8*)(addr),sizeof(*(val)),sizeof(*(val)),0)
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#endif
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#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
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static int indirect_write_config(struct pci_bus *pbus, unsigned int devfn, int where,
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int size, u32 value)
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{
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struct pci_controller *hose = pbus->sysdata;
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u8 cfg_type = 0;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(pbus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->set_cfg_type)
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if (pbus->number != hose->first_busno)
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cfg_type = 1;
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out_be32(hose->cfg_addr,
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(((where & 0xfc) | cfg_type) << 24) | (devfn << 16)
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| ((pbus->number - hose->bus_offset) << 8) | 0x80);
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switch (size)
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{
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case 1:
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cfg_write(value, hose->cfg_data + (where & 3), u8, out_8);
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break;
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case 2:
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cfg_write(value, hose->cfg_data + (where & 2), u16, out_le16);
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break;
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case 4:
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cfg_write(value, hose->cfg_data + (where & 0), u32, out_le32);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int indirect_read_config(struct pci_bus *pbus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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struct pci_controller *hose = pbus->sysdata;
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u8 cfg_type = 0;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(pbus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->set_cfg_type)
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if (pbus->number != hose->first_busno)
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cfg_type = 1;
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out_be32(hose->cfg_addr,
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(((where & 0xfc) | cfg_type) << 24) | (devfn << 16)
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| ((pbus->number - hose->bus_offset) << 8) | 0x80);
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switch (size)
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{
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case 1:
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cfg_read(value, hose->cfg_data + (where & 3), u8 *, in_8);
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break;
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case 2:
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cfg_read(value, hose->cfg_data + (where & 2), u16 *, in_le16);
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break;
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case 4:
|
|
cfg_read(value, hose->cfg_data + (where & 0), u32 *, in_le32);
|
|
break;
|
|
}
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static struct pci_ops indirect_pci_ops =
|
|
{
|
|
.read = indirect_read_config,
|
|
.write = indirect_write_config,
|
|
};
|
|
|
|
void
|
|
setup_m8260_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
|
|
{
|
|
hose->ops = &indirect_pci_ops;
|
|
hose->cfg_addr = (unsigned int *) ioremap(cfg_addr, 4);
|
|
hose->cfg_data = (unsigned char *) ioremap(cfg_data, 4);
|
|
}
|