![Russell King](/assets/img/avatar_default.png)
Rather than hard-coding the platform device IDs, enumerate them. We don't particularly care about the actual ID we get, just as long as they're unique. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
657 lines
16 KiB
C
657 lines
16 KiB
C
/*
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* arch/ppc/syslib/mpc10x_common.c
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*
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* Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
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* Mem ctlr, EPIC, etc.
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/serial_8250.h>
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#include <linux/fsl_devices.h>
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#include <linux/device.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/open_pic.h>
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#include <asm/mpc10x.h>
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#include <asm/ppc_sys.h>
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#ifdef CONFIG_MPC10X_OPENPIC
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#ifdef CONFIG_EPIC_SERIAL_MODE
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#define EPIC_IRQ_BASE (epic_serial_mode ? 16 : 5)
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#else
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#define EPIC_IRQ_BASE 5
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#endif
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#define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS)
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#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
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#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
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#define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS)
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#define MPC10X_UART1_IRQ (EPIC_IRQ_BASE + 5 + NUM_8259_INTERRUPTS)
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#else
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#define MPC10X_I2C_IRQ -1
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#define MPC10X_DMA0_IRQ -1
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#define MPC10X_DMA1_IRQ -1
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#define MPC10X_UART0_IRQ -1
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#define MPC10X_UART1_IRQ -1
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#endif
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static struct fsl_i2c_platform_data mpc10x_i2c_pdata = {
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.device_flags = 0,
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};
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static struct plat_serial8250_port serial_plat_uart0[] = {
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[0] = {
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.mapbase = 0x4500,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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},
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{ },
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};
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static struct plat_serial8250_port serial_plat_uart1[] = {
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[0] = {
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.mapbase = 0x4600,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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},
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{ },
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};
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struct platform_device ppc_sys_platform_devices[] = {
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[MPC10X_IIC1] = {
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.name = "fsl-i2c",
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.id = 1,
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.dev.platform_data = &mpc10x_i2c_pdata,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC10X_EUMB_I2C_OFFSET,
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.end = MPC10X_EUMB_I2C_OFFSET +
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MPC10X_EUMB_I2C_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.flags = IORESOURCE_IRQ
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},
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},
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},
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[MPC10X_DMA0] = {
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.name = "fsl-dma",
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.id = 0,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC10X_EUMB_DMA_OFFSET + 0x10,
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.end = MPC10X_EUMB_DMA_OFFSET + 0x1f,
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.flags = IORESOURCE_MEM,
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},
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{
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC10X_DMA1] = {
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.name = "fsl-dma",
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.id = 1,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC10X_EUMB_DMA_OFFSET + 0x20,
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.end = MPC10X_EUMB_DMA_OFFSET + 0x2f,
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.flags = IORESOURCE_MEM,
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},
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{
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC10X_DMA1] = {
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.name = "fsl-dma",
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.id = 1,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC10X_EUMB_DMA_OFFSET + 0x20,
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.end = MPC10X_EUMB_DMA_OFFSET + 0x2f,
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.flags = IORESOURCE_MEM,
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},
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{
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC10X_UART0] = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev.platform_data = serial_plat_uart0,
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},
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[MPC10X_UART1] = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM1,
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.dev.platform_data = serial_plat_uart1,
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},
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};
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/* We use the PCI ID to match on */
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struct ppc_sys_spec *cur_ppc_sys_spec;
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struct ppc_sys_spec ppc_sys_specs[] = {
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{
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.ppc_sys_name = "8245",
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.mask = 0xFFFFFFFF,
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.value = MPC10X_BRIDGE_8245,
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.num_devices = 5,
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.device_list = (enum ppc_sys_devices[])
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{
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MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_UART0, MPC10X_UART1,
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},
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},
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{
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.ppc_sys_name = "8240",
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.mask = 0xFFFFFFFF,
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.value = MPC10X_BRIDGE_8240,
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.num_devices = 3,
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.device_list = (enum ppc_sys_devices[])
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{
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MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
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},
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},
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{
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.ppc_sys_name = "107",
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.mask = 0xFFFFFFFF,
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.value = MPC10X_BRIDGE_107,
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.num_devices = 3,
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.device_list = (enum ppc_sys_devices[])
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{
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MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
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},
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},
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{ /* default match */
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.ppc_sys_name = "",
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.mask = 0x00000000,
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.value = 0x00000000,
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},
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};
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/*
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* mach_mpc10x_fixup: This function enables DUART mode if it detects
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* if it detects two UARTS in the platform device entries.
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*/
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static int __init mach_mpc10x_fixup(struct platform_device *pdev)
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{
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if (strncmp (pdev->name, "serial8250", 10) == 0 && pdev->id == 1)
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writeb(readb(serial_plat_uart1[0].membase + 0x11) | 0x1,
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serial_plat_uart1[0].membase + 0x11);
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return 0;
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}
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static int __init mach_mpc10x_init(void)
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{
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ppc_sys_device_fixup = mach_mpc10x_fixup;
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return 0;
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}
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postcore_initcall(mach_mpc10x_init);
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/* Set resources to match bridge memory map */
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void __init
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mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
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{
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switch (map) {
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case MPC10X_MEM_MAP_A:
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pci_init_resource(&hose->io_resource,
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0x00000000,
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0x3f7fffff,
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IORESOURCE_IO,
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"PCI host bridge");
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pci_init_resource (&hose->mem_resources[0],
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0xc0000000,
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0xfeffffff,
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IORESOURCE_MEM,
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"PCI host bridge");
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break;
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case MPC10X_MEM_MAP_B:
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pci_init_resource(&hose->io_resource,
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0x00000000,
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0x00bfffff,
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IORESOURCE_IO,
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"PCI host bridge");
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pci_init_resource (&hose->mem_resources[0],
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0x80000000,
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0xfcffffff,
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IORESOURCE_MEM,
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"PCI host bridge");
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break;
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default:
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printk("mpc10x_bridge_set_resources: "
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"Invalid map specified\n");
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if (ppc_md.progress)
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ppc_md.progress("mpc10x:exit1", 0x100);
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}
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}
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/*
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* Do some initialization and put the EUMB registers at the specified address
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* (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
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*
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* The EPIC is not on the 106, only the 8240 and 107.
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*/
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int __init
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mpc10x_bridge_init(struct pci_controller *hose,
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uint current_map,
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uint new_map,
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uint phys_eumb_base)
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{
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int host_bridge, picr1, picr1_bit, i;
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ulong pci_config_addr, pci_config_data;
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u_char pir, byte;
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if (ppc_md.progress) ppc_md.progress("mpc10x:enter", 0x100);
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/* Set up for current map so we can get at config regs */
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switch (current_map) {
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case MPC10X_MEM_MAP_A:
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setup_indirect_pci(hose,
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MPC10X_MAPA_CNFG_ADDR,
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MPC10X_MAPA_CNFG_DATA);
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break;
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case MPC10X_MEM_MAP_B:
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setup_indirect_pci(hose,
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MPC10X_MAPB_CNFG_ADDR,
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MPC10X_MAPB_CNFG_DATA);
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break;
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default:
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printk("mpc10x_bridge_init: %s\n",
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"Invalid current map specified");
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if (ppc_md.progress)
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ppc_md.progress("mpc10x:exit1", 0x100);
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return -1;
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}
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/* Make sure it's a supported bridge */
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early_read_config_dword(hose,
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0,
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PCI_DEVFN(0,0),
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PCI_VENDOR_ID,
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&host_bridge);
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switch (host_bridge) {
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case MPC10X_BRIDGE_106:
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case MPC10X_BRIDGE_8240:
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case MPC10X_BRIDGE_107:
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case MPC10X_BRIDGE_8245:
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break;
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default:
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if (ppc_md.progress)
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ppc_md.progress("mpc10x:exit2", 0x100);
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return -1;
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}
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switch (new_map) {
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case MPC10X_MEM_MAP_A:
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MPC10X_SETUP_HOSE(hose, A);
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pci_config_addr = MPC10X_MAPA_CNFG_ADDR;
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pci_config_data = MPC10X_MAPA_CNFG_DATA;
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picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_A;
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break;
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case MPC10X_MEM_MAP_B:
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MPC10X_SETUP_HOSE(hose, B);
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pci_config_addr = MPC10X_MAPB_CNFG_ADDR;
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pci_config_data = MPC10X_MAPB_CNFG_DATA;
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picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_B;
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break;
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default:
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printk("mpc10x_bridge_init: %s\n",
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"Invalid new map specified");
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if (ppc_md.progress)
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ppc_md.progress("mpc10x:exit3", 0x100);
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return -1;
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}
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/* Make bridge use the 'new_map', if not already usng it */
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if (current_map != new_map) {
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early_read_config_dword(hose,
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0,
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PCI_DEVFN(0,0),
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MPC10X_CFG_PICR1_REG,
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&picr1);
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picr1 = (picr1 & ~MPC10X_CFG_PICR1_ADDR_MAP_MASK) |
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picr1_bit;
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early_write_config_dword(hose,
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0,
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PCI_DEVFN(0,0),
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MPC10X_CFG_PICR1_REG,
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picr1);
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asm volatile("sync");
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/* Undo old mappings & map in new cfg data/addr regs */
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iounmap((void *)hose->cfg_addr);
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iounmap((void *)hose->cfg_data);
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setup_indirect_pci(hose,
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pci_config_addr,
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pci_config_data);
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}
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/* Setup resources to match map */
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mpc10x_bridge_set_resources(new_map, hose);
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/*
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* Want processor accesses of 0xFDxxxxxx to be mapped
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* to PCI memory space at 0x00000000. Do not want
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* host bridge to respond to PCI memory accesses of
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* 0xFDxxxxxx. Do not want host bridge to respond
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* to PCI memory addresses 0xFD000000-0xFDFFFFFF;
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* want processor accesses from 0x000A0000-0x000BFFFF
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* to be forwarded to system memory.
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*
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* Only valid if not in agent mode and using MAP B.
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*/
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if (new_map == MPC10X_MEM_MAP_B) {
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early_read_config_byte(hose,
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0,
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PCI_DEVFN(0,0),
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MPC10X_CFG_MAPB_OPTIONS_REG,
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&byte);
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byte &= ~(MPC10X_CFG_MAPB_OPTIONS_PFAE |
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MPC10X_CFG_MAPB_OPTIONS_PCICH |
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MPC10X_CFG_MAPB_OPTIONS_PROCCH);
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if (host_bridge != MPC10X_BRIDGE_106) {
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byte |= MPC10X_CFG_MAPB_OPTIONS_CFAE;
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}
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early_write_config_byte(hose,
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0,
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PCI_DEVFN(0,0),
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MPC10X_CFG_MAPB_OPTIONS_REG,
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byte);
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}
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if (host_bridge != MPC10X_BRIDGE_106) {
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early_read_config_byte(hose,
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0,
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PCI_DEVFN(0,0),
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MPC10X_CFG_PIR_REG,
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&pir);
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if (pir != MPC10X_CFG_PIR_HOST_BRIDGE) {
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printk("Host bridge in Agent mode\n");
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/* Read or Set LMBAR & PCSRBAR? */
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}
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/* Set base addr of the 8240/107 EUMB. */
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early_write_config_dword(hose,
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0,
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PCI_DEVFN(0,0),
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MPC10X_CFG_EUMBBAR,
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phys_eumb_base);
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#ifdef CONFIG_MPC10X_OPENPIC
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/* Map EPIC register part of EUMB into vitual memory - PCORE
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uses an i8259 instead of EPIC. */
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OpenPIC_Addr =
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ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET,
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MPC10X_EUMB_EPIC_SIZE);
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#endif
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}
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#ifdef CONFIG_MPC10X_STORE_GATHERING
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mpc10x_enable_store_gathering(hose);
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#else
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mpc10x_disable_store_gathering(hose);
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#endif
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/* setup platform devices for MPC10x bridges */
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identify_ppc_sys_by_id (host_bridge);
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for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) {
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unsigned int dev_id = cur_ppc_sys_spec->device_list[i];
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ppc_sys_fixup_mem_resource(&ppc_sys_platform_devices[dev_id],
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phys_eumb_base);
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}
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/* IRQ's are determined at runtime */
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ppc_sys_platform_devices[MPC10X_IIC1].resource[1].start = MPC10X_I2C_IRQ;
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ppc_sys_platform_devices[MPC10X_IIC1].resource[1].end = MPC10X_I2C_IRQ;
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ppc_sys_platform_devices[MPC10X_DMA0].resource[1].start = MPC10X_DMA0_IRQ;
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ppc_sys_platform_devices[MPC10X_DMA0].resource[1].end = MPC10X_DMA0_IRQ;
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ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ;
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ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ;
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serial_plat_uart0[0].mapbase += phys_eumb_base;
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serial_plat_uart0[0].irq = MPC10X_UART0_IRQ;
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serial_plat_uart0[0].membase = ioremap(serial_plat_uart0[0].mapbase, 0x100);
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serial_plat_uart1[0].mapbase += phys_eumb_base;
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serial_plat_uart1[0].irq = MPC10X_UART1_IRQ;
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serial_plat_uart1[0].membase = ioremap(serial_plat_uart1[0].mapbase, 0x100);
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/*
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* 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative
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* PCI reads may return stale data so turn off.
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*/
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if ((host_bridge == MPC10X_BRIDGE_8240)
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|| (host_bridge == MPC10X_BRIDGE_8245)
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|| (host_bridge == MPC10X_BRIDGE_107)) {
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early_read_config_dword(hose, 0, PCI_DEVFN(0,0),
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MPC10X_CFG_PICR1_REG, &picr1);
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picr1 &= ~MPC10X_CFG_PICR1_SPEC_PCI_RD;
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early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
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MPC10X_CFG_PICR1_REG, picr1);
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}
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/*
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* 8241/8245 erratum 28: PCI reads from local memory may return
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* stale data. Workaround by setting PICR2[0] to disable copyback
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* optimization. Oddly, the latest available user manual for the
|
|
* 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd.
|
|
*/
|
|
if (host_bridge == MPC10X_BRIDGE_8245) {
|
|
u32 picr2;
|
|
|
|
early_read_config_dword(hose, 0, PCI_DEVFN(0,0),
|
|
MPC10X_CFG_PICR2_REG, &picr2);
|
|
|
|
picr2 |= MPC10X_CFG_PICR2_COPYBACK_OPT;
|
|
|
|
early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
|
|
MPC10X_CFG_PICR2_REG, picr2);
|
|
}
|
|
|
|
if (ppc_md.progress) ppc_md.progress("mpc10x:exit", 0x100);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Need to make our own PCI config space access macros because
|
|
* mpc10x_get_mem_size() is called before the data structures are set up for
|
|
* the 'early_xxx' and 'indirect_xxx' routines to work.
|
|
* Assumes bus 0.
|
|
*/
|
|
#define MPC10X_CFG_read(val, addr, type, op) *val = op((type)(addr))
|
|
#define MPC10X_CFG_write(val, addr, type, op) op((type *)(addr), (val))
|
|
|
|
#define MPC10X_PCI_OP(rw, size, type, op, mask) \
|
|
static void \
|
|
mpc10x_##rw##_config_##size(uint *cfg_addr, uint *cfg_data, int devfn, int offset, type val) \
|
|
{ \
|
|
out_be32(cfg_addr, \
|
|
((offset & 0xfc) << 24) | (devfn << 16) \
|
|
| (0 << 8) | 0x80); \
|
|
MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op); \
|
|
return; \
|
|
}
|
|
|
|
MPC10X_PCI_OP(read, byte, u8 *, in_8, 3)
|
|
MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0)
|
|
#if 0 /* Not used */
|
|
MPC10X_PCI_OP(write, byte, u8, out_8, 3)
|
|
MPC10X_PCI_OP(read, word, u16 *, in_le16, 2)
|
|
MPC10X_PCI_OP(write, word, u16, out_le16, 2)
|
|
MPC10X_PCI_OP(write, dword, u32, out_le32, 0)
|
|
#endif
|
|
|
|
/*
|
|
* Read the memory controller registers to determine the amount of memory in
|
|
* the system. This assumes that the firmware has correctly set up the memory
|
|
* controller registers.
|
|
*/
|
|
unsigned long __init
|
|
mpc10x_get_mem_size(uint mem_map)
|
|
{
|
|
uint *config_addr, *config_data, val;
|
|
ulong start, end, total, offset;
|
|
int i;
|
|
u_char bank_enables;
|
|
|
|
switch (mem_map) {
|
|
case MPC10X_MEM_MAP_A:
|
|
config_addr = (uint *)MPC10X_MAPA_CNFG_ADDR;
|
|
config_data = (uint *)MPC10X_MAPA_CNFG_DATA;
|
|
break;
|
|
case MPC10X_MEM_MAP_B:
|
|
config_addr = (uint *)MPC10X_MAPB_CNFG_ADDR;
|
|
config_data = (uint *)MPC10X_MAPB_CNFG_DATA;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
mpc10x_read_config_byte(config_addr,
|
|
config_data,
|
|
PCI_DEVFN(0,0),
|
|
MPC10X_MCTLR_MEM_BANK_ENABLES,
|
|
&bank_enables);
|
|
|
|
total = 0;
|
|
|
|
for (i=0; i<8; i++) {
|
|
if (bank_enables & (1 << i)) {
|
|
offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0);
|
|
mpc10x_read_config_dword(config_addr,
|
|
config_data,
|
|
PCI_DEVFN(0,0),
|
|
offset,
|
|
&val);
|
|
start = (val >> ((i & 3) << 3)) & 0xff;
|
|
|
|
offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0);
|
|
mpc10x_read_config_dword(config_addr,
|
|
config_data,
|
|
PCI_DEVFN(0,0),
|
|
offset,
|
|
&val);
|
|
val = (val >> ((i & 3) << 3)) & 0x03;
|
|
start = (val << 28) | (start << 20);
|
|
|
|
offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0);
|
|
mpc10x_read_config_dword(config_addr,
|
|
config_data,
|
|
PCI_DEVFN(0,0),
|
|
offset,
|
|
&val);
|
|
end = (val >> ((i & 3) << 3)) & 0xff;
|
|
|
|
offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0);
|
|
mpc10x_read_config_dword(config_addr,
|
|
config_data,
|
|
PCI_DEVFN(0,0),
|
|
offset,
|
|
&val);
|
|
val = (val >> ((i & 3) << 3)) & 0x03;
|
|
end = (val << 28) | (end << 20) | 0xfffff;
|
|
|
|
total += (end - start + 1);
|
|
}
|
|
}
|
|
|
|
return total;
|
|
}
|
|
|
|
int __init
|
|
mpc10x_enable_store_gathering(struct pci_controller *hose)
|
|
{
|
|
uint picr1;
|
|
|
|
early_read_config_dword(hose,
|
|
0,
|
|
PCI_DEVFN(0,0),
|
|
MPC10X_CFG_PICR1_REG,
|
|
&picr1);
|
|
|
|
picr1 |= MPC10X_CFG_PICR1_ST_GATH_EN;
|
|
|
|
early_write_config_dword(hose,
|
|
0,
|
|
PCI_DEVFN(0,0),
|
|
MPC10X_CFG_PICR1_REG,
|
|
picr1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int __init
|
|
mpc10x_disable_store_gathering(struct pci_controller *hose)
|
|
{
|
|
uint picr1;
|
|
|
|
early_read_config_dword(hose,
|
|
0,
|
|
PCI_DEVFN(0,0),
|
|
MPC10X_CFG_PICR1_REG,
|
|
&picr1);
|
|
|
|
picr1 &= ~MPC10X_CFG_PICR1_ST_GATH_EN;
|
|
|
|
early_write_config_dword(hose,
|
|
0,
|
|
PCI_DEVFN(0,0),
|
|
MPC10X_CFG_PICR1_REG,
|
|
picr1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_MPC10X_OPENPIC
|
|
void __init mpc10x_set_openpic(void)
|
|
{
|
|
/* Map external IRQs */
|
|
openpic_set_sources(0, EPIC_IRQ_BASE, OpenPIC_Addr + 0x10200);
|
|
/* Skip reserved space and map i2c and DMA Ch[01] */
|
|
openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020);
|
|
/* Skip reserved space and map Message Unit Interrupt (I2O) */
|
|
openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0);
|
|
/* Skip reserved space and map Serial Interupts */
|
|
openpic_set_sources(EPIC_IRQ_BASE + 4, 2, OpenPIC_Addr + 0x11120);
|
|
|
|
openpic_init(NUM_8259_INTERRUPTS);
|
|
}
|
|
#endif
|