![Kumar Gala](/assets/img/avatar_default.png)
PowerPC 40x and Book-E processors support a watchdog timer at the processor core level. The timer has implementation dependent timeout frequencies that can be configured by software. One the first Watchdog timeout we get a critical exception. It is left to board specific code to determine what should happen at this point. If nothing is done and another timeout period expires the processor may attempt to reset the machine. Command line parameters: wdt=0 : disable watchdog (default) wdt=1 : enable watchdog wdt_period=N : N sets the value of the Watchdog Timer Period. The Watchdog Timer Period meaning is implementation specific. Check User Manual for the processor for more details. This patch is based off of work done by Takeharu Kato. Signed-off-by: Matt McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
297 lines
7 KiB
C
297 lines
7 KiB
C
/*
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*
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* Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
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*
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* Copyright 2000-2001 MontaVista Software Inc.
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* Completed implementation.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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* Frank Rowand <frank_rowand@mvista.com>
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* Debbie Chu <debbie_chu@mvista.com>
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* Further modifications by Armin Kuster
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*
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* Module name: ppc4xx_setup.c
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*
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/reboot.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/initrd.h>
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#include <linux/pci.h>
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#include <linux/rtc.h>
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#include <linux/console.h>
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#include <linux/ide.h>
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#include <linux/serial_reg.h>
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#include <linux/seq_file.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/kgdb.h>
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#include <asm/ibm4xx.h>
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#include <asm/time.h>
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#include <asm/todc.h>
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#include <asm/ppc4xx_pic.h>
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#include <asm/pci-bridge.h>
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#include <asm/bootinfo.h>
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#include <syslib/gen550.h>
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/* Function Prototypes */
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extern void abort(void);
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extern void ppc4xx_find_bridges(void);
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/* Global Variables */
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bd_t __res;
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void __init
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ppc4xx_setup_arch(void)
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{
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#if !defined(CONFIG_BDI_SWITCH)
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/*
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* The Abatron BDI JTAG debugger does not tolerate others
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* mucking with the debug registers.
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*/
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mtspr(SPRN_DBCR0, (DBCR0_IDM));
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mtspr(SPRN_DBSR, 0xffffffff);
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#endif
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/* Setup PCI host bridges */
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#ifdef CONFIG_PCI
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ppc4xx_find_bridges();
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#endif
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}
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/*
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* This routine pretty-prints the platform's internal CPU clock
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* frequencies into the buffer for usage in /proc/cpuinfo.
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*/
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static int
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ppc4xx_show_percpuinfo(struct seq_file *m, int i)
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{
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seq_printf(m, "clock\t\t: %ldMHz\n", (long)__res.bi_intfreq / 1000000);
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return 0;
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}
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/*
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* This routine pretty-prints the platform's internal bus clock
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* frequencies into the buffer for usage in /proc/cpuinfo.
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*/
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static int
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ppc4xx_show_cpuinfo(struct seq_file *m)
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{
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bd_t *bip = &__res;
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seq_printf(m, "machine\t\t: %s\n", PPC4xx_MACHINE_NAME);
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seq_printf(m, "plb bus clock\t: %ldMHz\n",
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(long) bip->bi_busfreq / 1000000);
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#ifdef CONFIG_PCI
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seq_printf(m, "pci bus clock\t: %dMHz\n",
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bip->bi_pci_busfreq / 1000000);
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#endif
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return 0;
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}
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/*
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* Return the virtual address representing the top of physical RAM.
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*/
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static unsigned long __init
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ppc4xx_find_end_of_memory(void)
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{
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return ((unsigned long) __res.bi_memsize);
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}
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void __init
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ppc4xx_map_io(void)
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{
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io_block_mapping(PPC4xx_ONB_IO_VADDR,
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PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO);
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#ifdef CONFIG_PCI
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io_block_mapping(PPC4xx_PCI_IO_VADDR,
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PPC4xx_PCI_IO_PADDR, PPC4xx_PCI_IO_SIZE, _PAGE_IO);
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io_block_mapping(PPC4xx_PCI_CFG_VADDR,
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PPC4xx_PCI_CFG_PADDR, PPC4xx_PCI_CFG_SIZE, _PAGE_IO);
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io_block_mapping(PPC4xx_PCI_LCFG_VADDR,
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PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO);
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#endif
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}
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void __init
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ppc4xx_init_IRQ(void)
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{
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ppc4xx_pic_init();
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}
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static void
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ppc4xx_restart(char *cmd)
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{
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printk("%s\n", cmd);
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abort();
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}
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static void
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ppc4xx_power_off(void)
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{
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printk("System Halted\n");
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local_irq_disable();
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while (1) ;
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}
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static void
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ppc4xx_halt(void)
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{
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printk("System Halted\n");
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local_irq_disable();
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while (1) ;
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}
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/*
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* This routine retrieves the internal processor frequency from the board
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* information structure, sets up the kernel timer decrementer based on
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* that value, enables the 4xx programmable interval timer (PIT) and sets
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* it up for auto-reload.
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*/
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static void __init
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ppc4xx_calibrate_decr(void)
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{
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unsigned int freq;
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bd_t *bip = &__res;
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#if defined(CONFIG_WALNUT) || defined(CONFIG_SYCAMORE)
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/* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
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mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
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#endif
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freq = bip->bi_tbfreq;
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tb_ticks_per_jiffy = freq / HZ;
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tb_to_us = mulhwu_scale_factor(freq, 1000000);
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/* Set the time base to zero.
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** At 200 Mhz, time base will rollover in ~2925 years.
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*/
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mtspr(SPRN_TBWL, 0);
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mtspr(SPRN_TBWU, 0);
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/* Clear any pending timer interrupts */
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mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS);
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mtspr(SPRN_TCR, TCR_PIE | TCR_ARE);
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/* Set the PIT reload value and just let it run. */
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mtspr(SPRN_PIT, tb_ticks_per_jiffy);
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}
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/*
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* IDE stuff.
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* should be generic for every IDE PCI chipset
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*/
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#if defined(CONFIG_PCI) && defined(CONFIG_IDE)
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static void
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ppc4xx_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
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unsigned long ctrl_port, int *irq)
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{
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int i;
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for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
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hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
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hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
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TODC_ALLOC();
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/*
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* Input(s):
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* r3 - Optional pointer to a board information structure.
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* r4 - Optional pointer to the physical starting address of the init RAM
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* disk.
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* r5 - Optional pointer to the physical ending address of the init RAM
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* disk.
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* r6 - Optional pointer to the physical starting address of any kernel
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* command-line parameters.
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* r7 - Optional pointer to the physical ending address of any kernel
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* command-line parameters.
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*/
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void __init
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ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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/*
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* If we were passed in a board information, copy it into the
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* residual data area.
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*/
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if (r3)
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__res = *(bd_t *)(r3 + KERNELBASE);
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#if defined(CONFIG_BLK_DEV_INITRD)
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/*
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* If the init RAM disk has been configured in, and there's a valid
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* starting address for it, set it up.
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*/
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if (r4) {
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initrd_start = r4 + KERNELBASE;
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initrd_end = r5 + KERNELBASE;
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}
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#endif /* CONFIG_BLK_DEV_INITRD */
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/* Copy the kernel command line arguments to a safe place. */
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if (r6) {
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*(char *) (r7 + KERNELBASE) = 0;
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strcpy(cmd_line, (char *) (r6 + KERNELBASE));
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}
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/* Initialize machine-dependent vectors */
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ppc_md.setup_arch = ppc4xx_setup_arch;
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ppc_md.show_percpuinfo = ppc4xx_show_percpuinfo;
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ppc_md.show_cpuinfo = ppc4xx_show_cpuinfo;
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ppc_md.init_IRQ = ppc4xx_init_IRQ;
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ppc_md.restart = ppc4xx_restart;
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ppc_md.power_off = ppc4xx_power_off;
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ppc_md.halt = ppc4xx_halt;
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ppc_md.calibrate_decr = ppc4xx_calibrate_decr;
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ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory;
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ppc_md.setup_io_mappings = ppc4xx_map_io;
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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ppc_md.progress = gen550_progress;
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#endif
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#if defined(CONFIG_PCI) && defined(CONFIG_IDE)
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ppc_ide_md.ide_init_hwif = ppc4xx_ide_init_hwif_ports;
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
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}
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/* Called from MachineCheckException */
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void platform_machine_check(struct pt_regs *regs)
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{
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#if defined(DCRN_PLB0_BEAR)
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printk("PLB0: BEAR= 0x%08x ACR= 0x%08x BESR= 0x%08x\n",
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mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_PLB0_ACR),
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mfdcr(DCRN_PLB0_BESR));
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#endif
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#if defined(DCRN_POB0_BEAR)
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printk("PLB0 to OPB: BEAR= 0x%08x BESR0= 0x%08x BESR1= 0x%08x\n",
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mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0),
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mfdcr(DCRN_POB0_BESR1));
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#endif
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}
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