![Kumar Gala](/assets/img/avatar_default.png)
Adds support for the two PCI busses on MPC83xx and the MPC834x SYS/PIBS reference board. The code initializes PCI inbound/outbound windows, allocates and registers PCI memory/io space. Be aware that setup of the PCI buses on the PIBs board is expected to be done by the firmware. Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
414 lines
11 KiB
C
414 lines
11 KiB
C
/*
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* arch/ppc/syslib/ppc83xx_setup.c
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*
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* MPC83XX common board code
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*
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* Maintainer: Kumar Gala <kumar.gala@freescale.com>
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Added PCI support -- Tony Li <tony.li@freescale.com>
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/serial.h>
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#include <linux/tty.h> /* for linux/serial_core.h */
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <asm/time.h>
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#include <asm/mpc83xx.h>
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#include <asm/mmu.h>
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#include <asm/ppc_sys.h>
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#include <asm/kgdb.h>
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#include <asm/delay.h>
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#include <syslib/ppc83xx_setup.h>
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#if defined(CONFIG_PCI)
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#include <asm/delay.h>
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#include <syslib/ppc83xx_pci.h>
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#endif
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phys_addr_t immrbar;
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/* Return the amount of memory */
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unsigned long __init
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mpc83xx_find_end_of_memory(void)
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{
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bd_t *binfo;
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binfo = (bd_t *) __res;
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return binfo->bi_memsize;
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}
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long __init
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mpc83xx_time_init(void)
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{
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#define SPCR_OFFS 0x00000110
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#define SPCR_TBEN 0x00400000
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bd_t *binfo = (bd_t *)__res;
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u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4);
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*spcr |= SPCR_TBEN;
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iounmap(spcr);
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return 0;
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}
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/* The decrementer counts at the system (internal) clock freq divided by 4 */
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void __init
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mpc83xx_calibrate_decr(void)
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{
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bd_t *binfo = (bd_t *) __res;
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unsigned int freq, divisor;
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freq = binfo->bi_busfreq;
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divisor = 4;
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tb_ticks_per_jiffy = freq / HZ / divisor;
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tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
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}
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#ifdef CONFIG_SERIAL_8250
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void __init
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mpc83xx_early_serial_map(void)
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{
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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struct uart_port serial_req;
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#endif
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struct plat_serial8250_port *pdata;
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bd_t *binfo = (bd_t *) __res;
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pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART);
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/* Setup serial port access */
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pdata[0].uartclk = binfo->bi_busfreq;
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pdata[0].mapbase += binfo->bi_immr_base;
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pdata[0].membase = ioremap(pdata[0].mapbase, 0x100);
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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memset(&serial_req, 0, sizeof (serial_req));
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serial_req.iotype = SERIAL_IO_MEM;
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serial_req.mapbase = pdata[0].mapbase;
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serial_req.membase = pdata[0].membase;
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serial_req.regshift = 0;
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gen550_init(0, &serial_req);
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#endif
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pdata[1].uartclk = binfo->bi_busfreq;
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pdata[1].mapbase += binfo->bi_immr_base;
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pdata[1].membase = ioremap(pdata[1].mapbase, 0x100);
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Assume gen550_init() doesn't modify serial_req */
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serial_req.mapbase = pdata[1].mapbase;
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serial_req.membase = pdata[1].membase;
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gen550_init(1, &serial_req);
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#endif
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}
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#endif
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void
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mpc83xx_restart(char *cmd)
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{
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volatile unsigned char __iomem *reg;
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unsigned char tmp;
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reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
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local_irq_disable();
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/*
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* Unlock the BCSR bits so a PRST will update the contents.
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* Otherwise the reset asserts but doesn't clear.
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*/
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tmp = in_8(reg + BCSR_MISC_REG3_OFF);
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tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
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out_8(reg + BCSR_MISC_REG3_OFF, tmp);
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/*
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* Trigger a reset via a low->high transition of the
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* PORESET bit.
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*/
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tmp = in_8(reg + BCSR_MISC_REG2_OFF);
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tmp &= ~BCSR_MISC_REG2_PORESET;
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out_8(reg + BCSR_MISC_REG2_OFF, tmp);
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udelay(1);
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tmp |= BCSR_MISC_REG2_PORESET;
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out_8(reg + BCSR_MISC_REG2_OFF, tmp);
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for(;;);
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}
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void
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mpc83xx_power_off(void)
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{
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local_irq_disable();
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for(;;);
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}
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void
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mpc83xx_halt(void)
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{
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local_irq_disable();
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for(;;);
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}
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#if defined(CONFIG_PCI)
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void __init
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mpc83xx_setup_pci1(struct pci_controller *hose)
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{
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u16 reg16;
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volatile immr_pcictrl_t * pci_ctrl;
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volatile immr_ios_t * ios;
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bd_t *binfo = (bd_t *) __res;
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pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t));
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ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
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/*
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* Configure PCI Outbound Translation Windows
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*/
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ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK;
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ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK;
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ios->pocmr0 = POCMR_EN |
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(((0xffffffff - (MPC83xx_PCI1_UPPER_MEM -
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MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
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/* mapped to PCI1 IO space */
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ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK;
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ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK;
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ios->pocmr1 = POCMR_EN | POCMR_IO |
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(((0xffffffff - (MPC83xx_PCI1_UPPER_IO -
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MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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pci_ctrl->pitar1 = 0x0;
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pci_ctrl->pibar1 = 0x0;
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pci_ctrl->piebar1 = 0x0;
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pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
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/*
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* Release PCI RST signal
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*/
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pci_ctrl->gcr = 0;
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udelay(2000);
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pci_ctrl->gcr = 1;
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udelay(2000);
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reg16 = 0xff;
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early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
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early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
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iounmap(pci_ctrl);
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iounmap(ios);
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}
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void __init
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mpc83xx_setup_pci2(struct pci_controller *hose)
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{
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u16 reg16;
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volatile immr_pcictrl_t * pci_ctrl;
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volatile immr_ios_t * ios;
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bd_t *binfo = (bd_t *) __res;
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pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
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ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
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/*
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* Configure PCI Outbound Translation Windows
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*/
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ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
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ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
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ios->pocmr3 = POCMR_EN | POCMR_DST |
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(((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
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MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
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/* mapped to PCI2 IO space */
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ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
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ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
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ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
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(((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
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MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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pci_ctrl->pitar1 = 0x0;
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pci_ctrl->pibar1 = 0x0;
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pci_ctrl->piebar1 = 0x0;
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pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
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/*
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* Release PCI RST signal
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*/
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pci_ctrl->gcr = 0;
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udelay(2000);
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pci_ctrl->gcr = 1;
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udelay(2000);
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reg16 = 0xff;
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early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
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early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
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iounmap(pci_ctrl);
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iounmap(ios);
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}
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/*
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* PCI buses can be enabled only if SYS board combinates with PIB
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* (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses
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* and 3 PCI slots, so people must configure the routes between them before
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* enable PCI bus. This routes are under the control of PCA9555PW device which
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* can be accessed via I2C bus 2 and are configured by firmware. Refer to
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* Freescale to get more information about firmware configuration.
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*/
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extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
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extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel,
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unsigned char pin);
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void __init
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mpc83xx_setup_hose(void)
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{
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u32 val32;
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volatile immr_clk_t * clk;
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struct pci_controller * hose1;
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#ifdef CONFIG_MPC83xx_PCI2
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struct pci_controller * hose2;
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#endif
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bd_t * binfo = (bd_t *)__res;
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clk = ioremap(binfo->bi_immr_base + 0xA00,
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sizeof(immr_clk_t));
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/*
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* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
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*/
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val32 = clk->occr;
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udelay(2000);
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clk->occr = 0xff000000;
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udelay(2000);
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iounmap(clk);
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hose1 = pcibios_alloc_controller();
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if(!hose1)
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return;
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = mpc83xx_map_irq;
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hose1->bus_offset = 0;
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hose1->first_busno = 0;
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hose1->last_busno = 0xff;
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setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
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binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
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hose1->set_cfg_type = 1;
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mpc83xx_setup_pci1(hose1);
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hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
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hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
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hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
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hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
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hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
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hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
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#ifdef CONFIG_MPC83xx_PCI2
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isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
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MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
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#else
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isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
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MPC83xx_PCI1_IO_SIZE);
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#endif /* CONFIG_MPC83xx_PCI2 */
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hose1->io_base_virt = (void *)isa_io_base;
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/* setup resources */
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pci_init_resource(&hose1->io_resource,
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MPC83xx_PCI1_LOWER_IO,
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MPC83xx_PCI1_UPPER_IO,
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IORESOURCE_IO, "PCI host bridge 1");
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pci_init_resource(&hose1->mem_resources[0],
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MPC83xx_PCI1_LOWER_MEM,
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MPC83xx_PCI1_UPPER_MEM,
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IORESOURCE_MEM, "PCI host bridge 1");
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ppc_md.pci_exclude_device = mpc83xx_exclude_device;
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hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
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#ifdef CONFIG_MPC83xx_PCI2
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hose2 = pcibios_alloc_controller();
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if(!hose2)
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return;
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hose2->bus_offset = hose1->last_busno + 1;
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hose2->first_busno = hose1->last_busno + 1;
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hose2->last_busno = 0xff;
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setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
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binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
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hose2->set_cfg_type = 1;
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mpc83xx_setup_pci2(hose2);
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hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
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hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
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hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
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hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
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hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
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hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
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hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
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/* setup resources */
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pci_init_resource(&hose2->io_resource,
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MPC83xx_PCI2_LOWER_IO,
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MPC83xx_PCI2_UPPER_IO,
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IORESOURCE_IO, "PCI host bridge 2");
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pci_init_resource(&hose2->mem_resources[0],
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MPC83xx_PCI2_LOWER_MEM,
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MPC83xx_PCI2_UPPER_MEM,
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IORESOURCE_MEM, "PCI host bridge 2");
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hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
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#endif /* CONFIG_MPC83xx_PCI2 */
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}
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#endif /*CONFIG_PCI*/
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