![Roman Zippel](/assets/img/avatar_default.png)
This finally renames the thread_info field in task structure to stack, so that the assumptions about this field are gone and archs have more freedom about placing the thread_info structure. Nonbroken archs which have a proper thread pointer can do the access to both current thread and task structure via a single pointer. It'll allow for a few more cleanups of the fork code, from which e.g. ia64 could benefit. Signed-off-by: Roman Zippel <zippel@linux-m68k.org> [akpm@linux-foundation.org: build fix] Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Ian Molton <spyro@f2s.com> Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> Cc: Mikael Starvik <starvik@axis.com> Cc: David Howells <dhowells@redhat.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Greg Ungerer <gerg@uclinux.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp> Cc: Richard Curnow <rc@rc0.org.uk> Cc: William Lee Irwin III <wli@holomorphy.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jeff Dike <jdike@addtoit.com> Cc: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> Cc: Miles Bader <uclinux-v850@lsi.nec.co.jp> Cc: Andi Kleen <ak@muc.de> Cc: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
166 lines
4.3 KiB
C
166 lines
4.3 KiB
C
#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#include <asm/cmpxchg.h>
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#ifdef __KERNEL__
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#define __STR(x) #x
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#define STR(x) __STR(x)
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#define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
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#define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
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/* frame pointer must be last for get_wchan */
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#define SAVE_CONTEXT "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
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#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
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#define __EXTRA_CLOBBER \
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,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
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/* Save restore flags to clear handle leaking NT */
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#define switch_to(prev,next,last) \
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asm volatile(SAVE_CONTEXT \
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"movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
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"movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
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"call __switch_to\n\t" \
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".globl thread_return\n" \
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"thread_return:\n\t" \
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"movq %%gs:%P[pda_pcurrent],%%rsi\n\t" \
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"movq %P[thread_info](%%rsi),%%r8\n\t" \
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LOCK_PREFIX "btr %[tif_fork],%P[ti_flags](%%r8)\n\t" \
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"movq %%rax,%%rdi\n\t" \
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"jc ret_from_fork\n\t" \
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RESTORE_CONTEXT \
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: "=a" (last) \
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: [next] "S" (next), [prev] "D" (prev), \
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[threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
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[ti_flags] "i" (offsetof(struct thread_info, flags)),\
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[tif_fork] "i" (TIF_FORK), \
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[thread_info] "i" (offsetof(struct task_struct, stack)), \
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[pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
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: "memory", "cc" __EXTRA_CLOBBER)
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extern void load_gs_index(unsigned);
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/*
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* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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*/
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#define loadsegment(seg,value) \
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asm volatile("\n" \
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"1:\t" \
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"movl %k0,%%" #seg "\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3:\t" \
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"movl %1,%%" #seg "\n\t" \
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"jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n\t" \
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".align 8\n\t" \
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".quad 1b,3b\n" \
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".previous" \
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: :"r" (value), "r" (0))
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/*
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* Clear and set 'TS' bit respectively
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*/
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#define clts() __asm__ __volatile__ ("clts")
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static inline unsigned long read_cr0(void)
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{
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unsigned long cr0;
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asm volatile("movq %%cr0,%0" : "=r" (cr0));
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return cr0;
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}
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static inline void write_cr0(unsigned long val)
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{
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asm volatile("movq %0,%%cr0" :: "r" (val));
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}
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static inline unsigned long read_cr3(void)
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{
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unsigned long cr3;
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asm("movq %%cr3,%0" : "=r" (cr3));
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return cr3;
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}
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static inline void write_cr3(unsigned long val)
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{
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asm volatile("movq %0,%%cr3" :: "r" (val) : "memory");
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}
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static inline unsigned long read_cr4(void)
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{
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unsigned long cr4;
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asm("movq %%cr4,%0" : "=r" (cr4));
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return cr4;
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}
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static inline void write_cr4(unsigned long val)
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{
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asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
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}
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#define stts() write_cr0(8 | read_cr0())
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#define wbinvd() \
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__asm__ __volatile__ ("wbinvd": : :"memory");
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*/
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static inline void sched_cacheflush(void)
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{
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wbinvd();
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}
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#endif /* __KERNEL__ */
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#define nop() __asm__ __volatile__ ("nop")
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() do {} while(0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do {} while(0)
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#endif
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#ifdef CONFIG_UNORDERED_IO
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#define wmb() asm volatile("sfence" ::: "memory")
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#else
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#define wmb() asm volatile("" ::: "memory")
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#endif
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#define read_barrier_depends() do {} while(0)
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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#define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
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#include <linux/irqflags.h>
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void cpu_idle_wait(void);
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extern unsigned long arch_align_stack(unsigned long sp);
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extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
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#endif
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