a7ca13826e
On the Aspeed chip, the GPIOs can be under control of the ARM chip or of the ColdFire coprocessor. (There's a third command source, the LPC bus, which we don't use or support yet). The control of which master is allowed to modify a given GPIO is per-bank (8 GPIOs). Unfortunately, systems already exist for which we want to use GPIOs of both sources in the same bank. This provides an API exported by the gpio-aspeed driver that an aspeed coprocessor driver can use to "grab" some GPIOs for use by the coprocessor, and allow the coprocessor driver to provide callbacks for arbitrating access. Once at least one GPIO of a given bank has been "grabbed" by the coprocessor, the entire bank is marked as being under coprocessor control. It's command source is switched to the coprocessor. If the ARM then tries to write to a GPIO in such a marked bank, the provided callbacks are used to request access from the coprocessor driver, which is responsible to doing whatever is necessary to "pause" the coprocessor or prevent it from trying to use the GPIOs while the ARM is doing its accesses. During that time, the command source for the bank is temporarily switched back to the ARM. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
16 lines
437 B
C
16 lines
437 B
C
#ifndef __GPIO_ASPEED_H
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#define __GPIO_ASPEED_H
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struct aspeed_gpio_copro_ops {
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int (*request_access)(void *data);
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int (*release_access)(void *data);
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};
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int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
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u16 *vreg_offset, u16 *dreg_offset, u8 *bit);
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int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc);
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int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data);
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#endif /* __GPIO_ASPEED_H */
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