b240d0143b
Both irqnum and irqarray properties reflect the same thing:
the number of bits and bytes for interrupts at this
chipset. E. g.:
irqnum = 8 x irqarray
This can be seen by the way pending interrupts are handled:
/* During probe time */
pmic->irqs = devm_kzalloc(dev, pmic->irqnum * sizeof(int), GFP_KERNEL);
/* While handling IRQs */
for (i = 0; i < pmic->irqarray; i++) {
pending = hi6421_spmi_pmic_read(pmic, (i + pmic->irq_addr));
pending &= 0xff;
for_each_set_bit(offset, &pending, 8)
generic_handle_irq(pmic->irqs[offset + i * 8]);
}
Going further, there are some logic at the driver which assumes
that irqarray is 2:
/* solve powerkey order */
if ((i == HISI_IRQ_KEY_NUM) &&
((pending & HISI_IRQ_KEY_VALUE) == HISI_IRQ_KEY_VALUE)) {
generic_handle_irq(pmic->irqs[HISI_IRQ_KEY_DOWN]);
generic_handle_irq(pmic->irqs[HISI_IRQ_KEY_UP]);
pending &= (~HISI_IRQ_KEY_VALUE);
}
As HISI_IRQ_KEY_DOWN and HISI_IRQ_KEY_UP are fixed values
and don't depend on irqnum/irqarray.
The IRQ addr and mask addr seem to be also fixed, based on some
comments at the OF parsing code. So, get rid of them too,
removing the of parsing function completely.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/e231244e42cb5b56240705cac2f987e11a078038.1597762400.git.mchehab+huawei@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
54 lines
1.1 KiB
C
54 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Header file for device driver Hi6421 PMIC
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*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (C) 2011 Hisilicon.
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*
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* Guodong Xu <guodong.xu@linaro.org>
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*/
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#ifndef __HISI_PMIC_H
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#define __HISI_PMIC_H
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#include <linux/irqdomain.h>
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#define HISI_REGS_ENA_PROTECT_TIME (0) /* in microseconds */
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#define HISI_ECO_MODE_ENABLE (1)
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#define HISI_ECO_MODE_DISABLE (0)
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struct hi6421_spmi_pmic {
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struct resource *res;
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struct device *dev;
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void __iomem *regs;
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spinlock_t lock;
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struct irq_domain *domain;
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int irq;
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int gpio;
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unsigned int *irqs;
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};
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int hi6421_spmi_pmic_read(struct hi6421_spmi_pmic *pmic, int reg);
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int hi6421_spmi_pmic_write(struct hi6421_spmi_pmic *pmic, int reg, u32 val);
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int hi6421_spmi_pmic_rmw(struct hi6421_spmi_pmic *pmic, int reg,
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u32 mask, u32 bits);
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enum hi6421_spmi_pmic_irq_list {
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OTMP = 0,
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VBUS_CONNECT,
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VBUS_DISCONNECT,
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ALARMON_R,
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HOLD_6S,
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HOLD_1S,
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POWERKEY_UP,
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POWERKEY_DOWN,
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OCP_SCP_R,
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COUL_R,
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SIM0_HPD_R,
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SIM0_HPD_F,
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SIM1_HPD_R,
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SIM1_HPD_F,
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PMIC_IRQ_LIST_MAX,
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};
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#endif /* __HISI_PMIC_H */
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