50c8308538
Currently, the following instructions are translated: - CACHE (indexed) - CACHE (va based): translated to a SYNCI, overkill on D-CACHE operations, but still much faster than a trap. - mfc0/mtc0: the virtual COP0 registers for the guest are implemented as 2-D array. [COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0. mfc0/mtc0 operations are transformed to load/stores. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
38 lines
980 B
C
38 lines
980 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* commpage, currently used for Virtual COP0 registers.
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* Mapped into the guest kernel @ 0x0.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/vmalloc.h>
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#include <linux/fs.h>
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#include <linux/bootmem.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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#include <linux/kvm_host.h>
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#include "kvm_mips_comm.h"
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void kvm_mips_commpage_init(struct kvm_vcpu *vcpu)
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{
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struct kvm_mips_commpage *page = vcpu->arch.kseg0_commpage;
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memset(page, 0, sizeof(struct kvm_mips_commpage));
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/* Specific init values for fields */
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vcpu->arch.cop0 = &page->cop0;
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memset(vcpu->arch.cop0, 0, sizeof(struct mips_coproc));
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return;
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}
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