76c9dd9dbd
This modifies the TI Davinci PLL clock driver to allow for the case when dev == NULL. On some (most) SoCs that use this driver, the PLL clock needs to be registered during early boot because it is used for clocksource/clkevent and there will be no platform device available. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com
72 lines
2.3 KiB
C
72 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PLL clock descriptions for TI DA830/OMAP-L137/AM17XX
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/clkdev.h>
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#include <linux/clk/davinci.h>
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include "pll.h"
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static const struct davinci_pll_clk_info da830_pll_info = {
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.name = "pll0",
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 4,
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.pllm_max = 32,
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.pllout_min_rate = 300000000,
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.pllout_max_rate = 600000000,
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.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
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};
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/*
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* NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
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* meaning that we could change the divider as long as we keep the correct
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* ratio between all of the clocks, but we don't support that because there is
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* currently not a need for it.
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*/
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SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
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SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
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SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
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SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
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SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
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SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
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int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
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clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
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clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1");
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
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clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0");
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
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clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0");
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clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1");
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
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clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1");
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
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clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0");
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
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clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
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clk_register_clkdev(clk, NULL, "i2c_davinci.1");
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clk_register_clkdev(clk, "timer0", NULL);
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clk_register_clkdev(clk, NULL, "davinci-wdt");
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return 0;
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}
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