98 lines
2.1 KiB
C
98 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* NWL MIPI DSI host driver
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*
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* Copyright (C) 2017 NXP
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* Copyright (C) 2019 Purism SPC
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*/
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#ifndef __NWL_DRV_H__
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#define __NWL_DRV_H__
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#include <linux/mux/consumer.h>
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#include <linux/phy/phy.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_mipi_dsi.h>
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struct nwl_dsi_platform_data;
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/* i.MX8 NWL quirks */
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/* i.MX8MQ errata E11418 */
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#define E11418_HS_MODE_QUIRK BIT(0)
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/* Skip DSI bits in SRC on disable to avoid blank display on enable */
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#define SRC_RESET_QUIRK BIT(1)
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/* * DPI color coding */
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#define NWL_DSI_DPI_16_BIT_565_PACKED 0
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#define NWL_DSI_DPI_16_BIT_565_ALIGNED 1
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#define NWL_DSI_DPI_16_BIT_565_SHIFTED 2
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#define NWL_DSI_DPI_18_BIT_PACKED 3
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#define NWL_DSI_DPI_18_BIT_ALIGNED 4
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#define NWL_DSI_DPI_24_BIT 5
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#define NWL_DSI_MAX_PLATFORM_CLOCKS 2
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struct nwl_dsi_plat_clk_config {
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const char *id;
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struct clk *clk;
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bool present;
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};
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struct mode_config {
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int clock;
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int crtc_clock;
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unsigned int lanes;
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unsigned long bitclock;
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unsigned long phy_rates[3];
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unsigned long pll_rates[3];
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int phy_rate_idx;
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struct list_head list;
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};
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struct nwl_dsi {
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struct drm_encoder encoder;
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struct drm_bridge bridge;
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struct mipi_dsi_host dsi_host;
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struct drm_bridge *panel_bridge;
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struct device *dev;
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struct phy *phy;
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union phy_configure_opts phy_cfg;
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unsigned int quirks;
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unsigned int instance;
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struct regmap *regmap;
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struct regmap *csr;
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int irq;
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struct reset_control *rst_byte;
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struct reset_control *rst_esc;
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struct reset_control *rst_dpi;
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struct reset_control *rst_pclk;
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struct mux_control *mux;
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/* DSI clocks */
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struct clk *phy_ref_clk;
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struct clk *rx_esc_clk;
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struct clk *tx_esc_clk;
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struct clk *pll_clk;
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struct clk *lcdif_clk;
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/* Platform dependent clocks */
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struct nwl_dsi_plat_clk_config clk_config[NWL_DSI_MAX_PLATFORM_CLOCKS];
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struct list_head valid_modes;
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/* dsi lanes */
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u32 lanes;
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u32 clk_drop_lvl;
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enum mipi_dsi_pixel_format format;
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struct drm_display_mode mode;
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unsigned long dsi_mode_flags;
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struct nwl_dsi_transfer *xfer;
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const struct nwl_dsi_platform_data *pdata;
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bool use_dcss;
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};
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#endif /* __NWL_DRV_H__ */
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