78c00ccc52
Now that the SPDX tag is in all fbtft files, that identifies the license in a specific and legally-defined manner. So the extra GPL text wording can be removed as it is no longer needed at all. This is done on a quest to remove the 700+ different ways that files in the kernel describe the GPL license text. And there's unneeded stuff like the address (sometimes incorrect) for the FSF which is never needed. No copyright headers or other non-license-description text was removed. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
270 lines
6.5 KiB
C
270 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* FB driver for the ILI9320 LCD Controller
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*
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* Copyright (C) 2013 Noralf Tronnes
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/gpio.h>
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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#include "fbtft.h"
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#define DRVNAME "fb_ili9320"
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#define WIDTH 240
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#define HEIGHT 320
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#define DEFAULT_GAMMA "07 07 6 0 0 0 5 5 4 0\n" \
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"07 08 4 7 5 1 2 0 7 7"
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static unsigned int read_devicecode(struct fbtft_par *par)
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{
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int ret;
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u8 rxbuf[8] = {0, };
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write_reg(par, 0x0000);
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ret = par->fbtftops.read(par, rxbuf, 4);
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return (rxbuf[2] << 8) | rxbuf[3];
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}
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static int init_display(struct fbtft_par *par)
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{
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unsigned int devcode;
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par->fbtftops.reset(par);
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devcode = read_devicecode(par);
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fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n",
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devcode);
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if ((devcode != 0x0000) && (devcode != 0x9320))
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dev_warn(par->info->device,
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"Unrecognized Device code: 0x%04X (expected 0x9320)\n",
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devcode);
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/* Initialization sequence from ILI9320 Application Notes */
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/* *********** Start Initial Sequence ********* */
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/* Set the Vcore voltage and this setting is must. */
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write_reg(par, 0x00E5, 0x8000);
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/* Start internal OSC. */
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write_reg(par, 0x0000, 0x0001);
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/* set SS and SM bit */
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write_reg(par, 0x0001, 0x0100);
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/* set 1 line inversion */
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write_reg(par, 0x0002, 0x0700);
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/* Resize register */
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write_reg(par, 0x0004, 0x0000);
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/* set the back and front porch */
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write_reg(par, 0x0008, 0x0202);
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/* set non-display area refresh cycle */
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write_reg(par, 0x0009, 0x0000);
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/* FMARK function */
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write_reg(par, 0x000A, 0x0000);
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/* RGB interface setting */
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write_reg(par, 0x000C, 0x0000);
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/* Frame marker Position */
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write_reg(par, 0x000D, 0x0000);
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/* RGB interface polarity */
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write_reg(par, 0x000F, 0x0000);
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/* ***********Power On sequence *************** */
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/* SAP, BT[3:0], AP, DSTB, SLP, STB */
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write_reg(par, 0x0010, 0x0000);
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/* DC1[2:0], DC0[2:0], VC[2:0] */
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write_reg(par, 0x0011, 0x0007);
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/* VREG1OUT voltage */
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write_reg(par, 0x0012, 0x0000);
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/* VDV[4:0] for VCOM amplitude */
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write_reg(par, 0x0013, 0x0000);
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/* Dis-charge capacitor power voltage */
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mdelay(200);
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/* SAP, BT[3:0], AP, DSTB, SLP, STB */
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write_reg(par, 0x0010, 0x17B0);
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/* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */
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write_reg(par, 0x0011, 0x0031);
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mdelay(50);
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/* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */
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write_reg(par, 0x0012, 0x0138);
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mdelay(50);
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/* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */
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write_reg(par, 0x0013, 0x1800);
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/* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */
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write_reg(par, 0x0029, 0x0008);
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mdelay(50);
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/* GRAM horizontal Address */
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write_reg(par, 0x0020, 0x0000);
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/* GRAM Vertical Address */
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write_reg(par, 0x0021, 0x0000);
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/* ------------------ Set GRAM area --------------- */
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/* Horizontal GRAM Start Address */
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write_reg(par, 0x0050, 0x0000);
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/* Horizontal GRAM End Address */
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write_reg(par, 0x0051, 0x00EF);
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/* Vertical GRAM Start Address */
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write_reg(par, 0x0052, 0x0000);
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/* Vertical GRAM End Address */
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write_reg(par, 0x0053, 0x013F);
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/* Gate Scan Line */
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write_reg(par, 0x0060, 0x2700);
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/* NDL,VLE, REV */
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write_reg(par, 0x0061, 0x0001);
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/* set scrolling line */
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write_reg(par, 0x006A, 0x0000);
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/* -------------- Partial Display Control --------- */
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write_reg(par, 0x0080, 0x0000);
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write_reg(par, 0x0081, 0x0000);
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write_reg(par, 0x0082, 0x0000);
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write_reg(par, 0x0083, 0x0000);
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write_reg(par, 0x0084, 0x0000);
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write_reg(par, 0x0085, 0x0000);
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/* -------------- Panel Control ------------------- */
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write_reg(par, 0x0090, 0x0010);
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write_reg(par, 0x0092, 0x0000);
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write_reg(par, 0x0093, 0x0003);
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write_reg(par, 0x0095, 0x0110);
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write_reg(par, 0x0097, 0x0000);
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write_reg(par, 0x0098, 0x0000);
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write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */
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return 0;
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}
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static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
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{
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switch (par->info->var.rotate) {
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/* R20h = Horizontal GRAM Start Address */
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/* R21h = Vertical GRAM Start Address */
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case 0:
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write_reg(par, 0x0020, xs);
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write_reg(par, 0x0021, ys);
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break;
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case 180:
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write_reg(par, 0x0020, WIDTH - 1 - xs);
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write_reg(par, 0x0021, HEIGHT - 1 - ys);
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break;
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case 270:
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write_reg(par, 0x0020, WIDTH - 1 - ys);
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write_reg(par, 0x0021, xs);
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break;
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case 90:
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write_reg(par, 0x0020, ys);
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write_reg(par, 0x0021, HEIGHT - 1 - xs);
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break;
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}
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write_reg(par, 0x0022); /* Write Data to GRAM */
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}
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static int set_var(struct fbtft_par *par)
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{
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switch (par->info->var.rotate) {
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case 0:
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write_reg(par, 0x3, (par->bgr << 12) | 0x30);
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break;
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case 270:
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write_reg(par, 0x3, (par->bgr << 12) | 0x28);
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break;
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case 180:
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write_reg(par, 0x3, (par->bgr << 12) | 0x00);
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break;
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case 90:
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write_reg(par, 0x3, (par->bgr << 12) | 0x18);
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break;
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}
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return 0;
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}
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/*
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* Gamma string format:
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* VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
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* VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
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*/
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#define CURVE(num, idx) curves[num * par->gamma.num_values + idx]
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static int set_gamma(struct fbtft_par *par, u32 *curves)
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{
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unsigned long mask[] = {
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0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
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0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
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};
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int i, j;
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/* apply mask */
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for (i = 0; i < 2; i++)
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for (j = 0; j < 10; j++)
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CURVE(i, j) &= mask[i * par->gamma.num_values + j];
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write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
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write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
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write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
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write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
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write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
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write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
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write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
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write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
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write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
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write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));
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return 0;
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}
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#undef CURVE
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static struct fbtft_display display = {
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.regwidth = 16,
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.width = WIDTH,
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.height = HEIGHT,
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.gamma_num = 2,
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.gamma_len = 10,
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.gamma = DEFAULT_GAMMA,
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.fbtftops = {
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.init_display = init_display,
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.set_addr_win = set_addr_win,
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.set_var = set_var,
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.set_gamma = set_gamma,
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},
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};
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FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);
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MODULE_ALIAS("spi:" DRVNAME);
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MODULE_ALIAS("platform:" DRVNAME);
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MODULE_ALIAS("spi:ili9320");
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MODULE_ALIAS("platform:ili9320");
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MODULE_DESCRIPTION("FB driver for the ILI9320 LCD Controller");
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MODULE_AUTHOR("Noralf Tronnes");
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MODULE_LICENSE("GPL");
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