d5aabbcaee
Board-related updates. This branch is getting smaller and smaller, which is the whole idea so that's reassuring. Right now by far most of the code is related to shmobile updates, and they are now switching over to removal of board code and migration to multiplatform, so we'll see their board code base shrink in the near future too, I hope. In addition to that is some defconfig updates, some display updates for OMAP and a bit of new board support for Rockchip boards. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSgBsmAAoJEIwa5zzehBx3m3oP/ingw9VE69O3GLjd2zWI35HJ +NuFmwlWFj+1XLysfCxHJn3rvkMJKM33ZcP6FkgJGMHfQRRBmrC0REG/nQq59riE c7R+Jguw044kAGH3evg4kCJ3gI+WD+H+juKf4IQ9bYDaneZGN9f0hkuzLRbmqwZP RIDa+q+Oo6Q3pcTUvkz2lMV6q7Ydb5H49suyPN+9muJ1wVYjFR+XuvnYzy/PO2lF kyIN2fijQN278QjM6eZEtsFoB7L7NmuZr8ZBTkekHSfybqIsb59JEqZER7huJSdR fEk0VQ/A6M2LQSRTL+UrCadFYaxDnW8wjxbpLUikhg7ONnrCBSGvVj4nFiEKAFdE R49YZ2hqhrXjie1kGoKuXGmxGG/7ODJWmWDgnIXx0daSOgPUomlO8YKtGeBO1/Zf 6wsvAjiukcLV10JEF/rCslTEA/Ck5dJZjV6S/8hSy1N+CF4qZflSmXG0gb9tB+nv ztRN9gTlJSr/MpIE3jpbPFxNwef+UPW/R8fnO7fdnzPeOpwTDzZ1ydArC0IIpmgt Ngum5iyP4qcwZ91hWXhdAu3ZGeHWZ5tox1W/DMjkyTxCEDUUdtfkChOGf/Wmjg7z Rl5nyH2Y4xT0+Otn/0LIqKvEh1JwwX9FlIqkJI4IMrnYJwHQ4oBvOAGskW1ZsFPQ 0OBbAAHS1tio3ZywNMIQ =ZYOa -----END PGP SIGNATURE----- Merge tag 'boards-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC board updates from Olof Johansson: "Board-related updates. This branch is getting smaller and smaller, which is the whole idea so that's reassuring. Right now by far most of the code is related to shmobile updates, and they are now switching over to removal of board code and migration to multiplatform, so we'll see their board code base shrink in the near future too, I hope. In addition to that is some defconfig updates, some display updates for OMAP and a bit of new board support for Rockchip boards" * tag 'boards-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (56 commits) ARM: rockchip: add support for rk3188 and Radxa Rock board ARM: rockchip: add dts for bqcurie2 tablet ARM: rockchip: enable arm-global-timer ARM: rockchip: move shared dt properties to common source file ARM: OMAP2+: display: Create omap_vout device inside omap_display_init ARM: OMAP2+: display: Create omapvrfb and omapfb devices inside omap_display_init ARM: OMAP2+: display: Create omapdrm device inside omap_display_init ARM: OMAP2+: drm: Don't build device for DMM ARM: tegra: defconfig updates RX-51: Add support for OMAP3 ROM Random Number Generator ARM: OMAP3: RX-51: ARM errata 430973 workaround ARM: OMAP3: Add secure function omap_smc3() which calling instruction smc #1 ARM: shmobile: marzen: enable INTC IRQ ARM: shmobile: bockw: add SMSC support on reference ARM: shmobile: Use SMP on Koelsch ARM: shmobile: Remove KZM9D reference DTS ARM: shmobile: Let KZM9D multiplatform boot with KZM9D DTB ARM: shmobile: Remove non-multiplatform KZM9D reference support ARM: shmobile: Use KZM9D without reference for multiplatform ARM: shmobile: Sync KZM9D DTS with KZM9D reference DTS ...
273 lines
6.4 KiB
Plaintext
273 lines
6.4 KiB
Plaintext
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3xxx.dtsi"
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#include "rk3066a-clocks.dtsi"
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/ {
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compatible = "rockchip,rk3066a";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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};
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soc {
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timer@20038000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x20038000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates1 0>, <&clk_gates7 7>;
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clock-names = "timer", "pclk";
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};
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timer@2003a000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2003a000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates1 1>, <&clk_gates7 8>;
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clock-names = "timer", "pclk";
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};
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timer@2000e000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2000e000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates1 2>, <&clk_gates7 9>;
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clock-names = "timer", "pclk";
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};
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pinctrl@20008000 {
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compatible = "rockchip,rk3066a-pinctrl";
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reg = <0x20008000 0x150>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@20034000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20034000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 9>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 10>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@2003e000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 11>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 12>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio4@20084000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20084000 0x100>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 13>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio6@2000a000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 15>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_default: pcfg_pull_default {
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bias-pull-pin-default;
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};
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pcfg_pull_none: pcfg_pull_none {
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bias-disable;
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart1_cts: uart1-cts {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart1_rts: uart1-rts {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
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};
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/* no rts / cts for uart2 */
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};
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uart3 {
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uart3_xfer: uart3-xfer {
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rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart3_cts: uart3-cts {
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rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart3_rts: uart3-rts {
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rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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sd0 {
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sd0_clk: sd0-clk {
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rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_cmd: sd0-cmd {
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rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_cd: sd0-cd {
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rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_wp: sd0-wp {
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rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_bus1: sd0-bus-width1 {
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rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_bus4: sd0-bus-width4 {
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rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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sd1 {
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sd1_clk: sd1-clk {
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rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_cmd: sd1-cmd {
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rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_cd: sd1-cd {
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rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_wp: sd1-wp {
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rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_bus1: sd1-bus-width1 {
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rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_bus4: sd1-bus-width4 {
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rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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};
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};
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};
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