d7d1d45cc4
This patch splits the sama5d3 SoCs definition: - a common base for all sama5d3 SoCs (sama5d3.dtsi) - several optional peripheral definitions which will be included by sama5d3 specific SoCs (sama5d3_'periph name'.dtsi) - sama5d3 specific SoC definitions (sama5d3x.dtsi) This provides a better representation of the real hardware (drop unneed dt nodes) and avoids peripheral id conflict (which is not the case for current sama5d3 SoCs, but could be if other SoCs of this family are released). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> [nicolas.ferre@atmel.com: add more "sama5d3?" compatibility strings] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
55 lines
1.4 KiB
Plaintext
55 lines
1.4 KiB
Plaintext
/*
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* at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
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* CAN support
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* Licensed under GPLv2.
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*/
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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ahb {
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apb {
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pinctrl@fffff200 {
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can0 {
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pinctrl_can0_rx_tx: can0_rx_tx {
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atmel,pins =
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<AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
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AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
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};
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};
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can1 {
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pinctrl_can1_rx_tx: can1_rx_tx {
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atmel,pins =
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<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
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AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
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};
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};
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};
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can0: can@f000c000 {
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compatible = "atmel,at91sam9x5-can";
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reg = <0xf000c000 0x300>;
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0_rx_tx>;
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status = "disabled";
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};
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can1: can@f8010000 {
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compatible = "atmel,at91sam9x5-can";
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reg = <0xf8010000 0x300>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1_rx_tx>;
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status = "disabled";
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};
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};
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};
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};
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