87ee15ec26
Looks like I made a typo on the control base, all the 81xx
SoCs have it at 0x48140000 base. We've just gotten away with
the typo as the Ethernet phy was configured by the bootloader
on my test system and we're not yet using the pinctrl.
In addition to fixing the contol base, we need to also use the
right Ethernet phy flags to initialize it. And we are still
missing the PLL driver for dm814x and only relying on the
divider and mux clocks.
Fixes: f3d953ea37 ("ARM: dts: Add minimal dm814x support")
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
29 lines
530 B
Plaintext
29 lines
530 B
Plaintext
/*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
#include "dm814x.dtsi"
|
|
|
|
/ {
|
|
model = "DM8148 EVM";
|
|
compatible = "ti,dm8148-evm", "ti,dm8148";
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x40000000>; /* 1 GB */
|
|
};
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy_id = <&davinci_mdio>, <0>;
|
|
phy-mode = "rgmii";
|
|
};
|
|
|
|
&cpsw_emac1 {
|
|
phy_id = <&davinci_mdio>, <1>;
|
|
phy-mode = "rgmii";
|
|
};
|