b3a5af435a
This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - Cleanups for Renesas shmobile platforms - Lots of added devices on LPC18xx - Lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5OMWAAoJEIwa5zzehBx3r2QP/1skn0zzgfvbK0kkPOh9q3Jk jX1elN4Wde1SnScz8UbdVb9nmdbhxsuYE/3+Lz7yCndWScBiak4qcsNHrSRhh3FA ST7Ub8DLc2TxY9K7eDkyVCcNkP35+UQTHCN76R5Lgrlfw3UO9Zr3xPFX3+Kd6aWz 9X8UnvJacQQIN/vO6J02kB96sKPEIANfuMgO6vDSbmcZ1RrdlHzjoRwAV0smECtJ NyOh+NQdPBR0gSl/peyKzAXoDHNXpDotltTmIz3tPA+dYBO/qG//B73H/oqox0ql AKAktyaDzdxXEuixPtAroo4dDy3xuIQ6xU+DNhPWQq0BgaxHWqkwq60d74ot8vCz 8gvC8pwA6gavbqVFNePOnwPNSyWZX01scX4fp903NjVM8/rGPvCR4y6p8lFIyVkG P0L8rmY/UYq3fieaAb1W0odASDrQpgg3zsHD7to43hz6jaRnMRCpA8nTVqJcyHqI E6YfGQH87Kpbvkjo0FYqo5P6xCCRTq+QUys6JruNYg05R/gd8AG7cXaVNO3yvg3T lRwNXDBt/zcp2exKnGR0IdGMUMICzsuoB8ZePkQdIWwePrd4AzT5qYJe/txmg1rd q+9VJqQkeF+txLd9XUV2W/Hcuzu3ZPCbs97I9tTKQHMGwKUZaPfuk2r4+4K+Ps5a dYwdms39p6AIT43rK+m3 =D2Pm -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
587 lines
14 KiB
Plaintext
587 lines
14 KiB
Plaintext
/*
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* Copyright 2012 Sascha Hauer, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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#include "imx27-pinfunc.h"
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#include <dt-bindings/clock/imx27-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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aliases {
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ethernet0 = &fec;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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spi0 = &cspi1;
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spi1 = &cspi2;
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spi2 = &cspi3;
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};
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aitc: aitc-interrupt-controller@e0000000 {
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compatible = "fsl,imx27-aitc", "fsl,avic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x10040000 0x1000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc26m {
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compatible = "fsl,imx-osc26m", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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};
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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operating-points = <
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/* kHz uV */
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266000 1300000
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399000 1450000
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>;
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clock-latency = <62500>;
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clocks = <&clks IMX27_CLK_CPU_DIV>;
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voltage-tolerance = <5>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&aitc>;
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ranges;
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aipi@10000000 { /* AIPI1 */
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10000000 0x20000>;
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ranges;
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dma: dma@10001000 {
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compatible = "fsl,imx27-dma";
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reg = <0x10001000 0x1000>;
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interrupts = <32>;
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clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
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<&clks IMX27_CLK_DMA_AHB_GATE>;
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clock-names = "ipg", "ahb";
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#dma-cells = <1>;
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#dma-channels = <16>;
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};
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wdog: wdog@10002000 {
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compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
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reg = <0x10002000 0x1000>;
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interrupts = <27>;
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clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
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};
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gpt1: timer@10003000 {
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compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
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reg = <0x10003000 0x1000>;
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interrupts = <26>;
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clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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gpt2: timer@10004000 {
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compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
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reg = <0x10004000 0x1000>;
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interrupts = <25>;
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clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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gpt3: timer@10005000 {
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compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
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reg = <0x10005000 0x1000>;
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interrupts = <24>;
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clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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pwm: pwm@10006000 {
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#pwm-cells = <2>;
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compatible = "fsl,imx27-pwm";
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reg = <0x10006000 0x1000>;
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interrupts = <23>;
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clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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rtc: rtc@10007000 {
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compatible = "fsl,imx21-rtc";
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reg = <0x10007000 0x1000>;
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interrupts = <22>;
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clocks = <&clks IMX27_CLK_CKIL>,
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<&clks IMX27_CLK_RTC_IPG_GATE>;
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clock-names = "ref", "ipg";
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};
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kpp: kpp@10008000 {
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compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
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reg = <0x10008000 0x1000>;
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interrupts = <21>;
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clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
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status = "disabled";
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};
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owire: owire@10009000 {
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compatible = "fsl,imx27-owire", "fsl,imx21-owire";
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reg = <0x10009000 0x1000>;
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clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
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status = "disabled";
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart2: serial@1000b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000b000 0x1000>;
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interrupts = <19>;
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clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart3: serial@1000c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000c000 0x1000>;
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interrupts = <18>;
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clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart4: serial@1000d000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000d000 0x1000>;
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interrupts = <17>;
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clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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cspi1: cspi@1000e000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x1000e000 0x1000>;
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interrupts = <16>;
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clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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cspi2: cspi@1000f000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x1000f000 0x1000>;
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interrupts = <15>;
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clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ssi1: ssi@10010000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
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reg = <0x10010000 0x1000>;
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interrupts = <14>;
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clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
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dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
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dma-names = "rx0", "tx0", "rx1", "tx1";
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fsl,fifo-depth = <8>;
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status = "disabled";
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};
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ssi2: ssi@10011000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
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reg = <0x10011000 0x1000>;
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interrupts = <13>;
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clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
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dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
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dma-names = "rx0", "tx0", "rx1", "tx1";
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fsl,fifo-depth = <8>;
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status = "disabled";
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};
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i2c1: i2c@10012000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
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reg = <0x10012000 0x1000>;
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interrupts = <12>;
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clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
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status = "disabled";
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};
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sdhci1: sdhci@10013000 {
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compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
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reg = <0x10013000 0x1000>;
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interrupts = <11>;
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clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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dmas = <&dma 7>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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sdhci2: sdhci@10014000 {
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compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
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reg = <0x10014000 0x1000>;
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interrupts = <10>;
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clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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dmas = <&dma 6>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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iomuxc: iomuxc@10015000 {
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compatible = "fsl,imx27-iomuxc";
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reg = <0x10015000 0x600>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio1: gpio@10015000 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015000 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@10015100 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015100 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@10015200 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015200 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@10015300 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015300 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@10015400 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015400 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio@10015500 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015500 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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audmux: audmux@10016000 {
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compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
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reg = <0x10016000 0x1000>;
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clocks = <&clks IMX27_CLK_DUMMY>;
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clock-names = "audmux";
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status = "disabled";
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};
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cspi3: cspi@10017000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x10017000 0x1000>;
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interrupts = <6>;
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clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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gpt4: timer@10019000 {
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compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
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reg = <0x10019000 0x1000>;
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interrupts = <4>;
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clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
|
|
|
|
gpt5: timer@1001a000 {
|
|
compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
|
|
reg = <0x1001a000 0x1000>;
|
|
interrupts = <3>;
|
|
clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
uart5: serial@1001b000 {
|
|
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
|
reg = <0x1001b000 0x1000>;
|
|
interrupts = <49>;
|
|
clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@1001c000 {
|
|
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
|
reg = <0x1001c000 0x1000>;
|
|
interrupts = <48>;
|
|
clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@1001d000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
|
|
reg = <0x1001d000 0x1000>;
|
|
interrupts = <1>;
|
|
clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci3: sdhci@1001e000 {
|
|
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
|
|
reg = <0x1001e000 0x1000>;
|
|
interrupts = <9>;
|
|
clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER2_GATE>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&dma 36>;
|
|
dma-names = "rx-tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt6: timer@1001f000 {
|
|
compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
|
|
reg = <0x1001f000 0x1000>;
|
|
interrupts = <2>;
|
|
clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
|
|
<&clks IMX27_CLK_PER1_GATE>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
};
|
|
|
|
aipi@10020000 { /* AIPI2 */
|
|
compatible = "fsl,aipi-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x10020000 0x20000>;
|
|
ranges;
|
|
|
|
fb: fb@10021000 {
|
|
compatible = "fsl,imx27-fb", "fsl,imx21-fb";
|
|
interrupts = <61>;
|
|
reg = <0x10021000 0x1000>;
|
|
clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
|
|
<&clks IMX27_CLK_LCDC_AHB_GATE>,
|
|
<&clks IMX27_CLK_PER3_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
coda: coda@10023000 {
|
|
compatible = "fsl,imx27-vpu", "cnm,codadx6";
|
|
reg = <0x10023000 0x0200>;
|
|
interrupts = <53>;
|
|
clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
|
|
<&clks IMX27_CLK_VPU_AHB_GATE>;
|
|
clock-names = "per", "ahb";
|
|
iram = <&iram>;
|
|
};
|
|
|
|
usbotg: usb@10024000 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024000 0x200>;
|
|
interrupts = <56>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh1: usb@10024200 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024200 0x200>;
|
|
interrupts = <54>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh2: usb@10024400 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024400 0x200>;
|
|
interrupts = <55>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
|
fsl,usbmisc = <&usbmisc 2>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@10024600 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx27-usbmisc";
|
|
reg = <0x10024600 0x200>;
|
|
clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
|
|
};
|
|
|
|
sahara2: sahara@10025000 {
|
|
compatible = "fsl,imx27-sahara";
|
|
reg = <0x10025000 0x1000>;
|
|
interrupts = <59>;
|
|
clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
|
|
<&clks IMX27_CLK_SAHARA_AHB_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
};
|
|
|
|
clks: ccm@10027000{
|
|
compatible = "fsl,imx27-ccm";
|
|
reg = <0x10027000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
iim: iim@10028000 {
|
|
compatible = "fsl,imx27-iim";
|
|
reg = <0x10028000 0x1000>;
|
|
interrupts = <62>;
|
|
clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
|
|
};
|
|
|
|
fec: ethernet@1002b000 {
|
|
compatible = "fsl,imx27-fec";
|
|
reg = <0x1002b000 0x1000>;
|
|
interrupts = <50>;
|
|
clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
|
|
<&clks IMX27_CLK_FEC_AHB_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
nfc: nand@d8000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx27-nand";
|
|
reg = <0xd8000000 0x1000>;
|
|
interrupts = <29>;
|
|
clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
weim: weim@d8002000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx27-weim";
|
|
reg = <0xd8002000 0x1000>;
|
|
clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
|
|
ranges = <
|
|
0 0 0xc0000000 0x08000000
|
|
1 0 0xc8000000 0x08000000
|
|
2 0 0xd0000000 0x02000000
|
|
3 0 0xd2000000 0x02000000
|
|
4 0 0xd4000000 0x02000000
|
|
5 0 0xd6000000 0x02000000
|
|
>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iram: iram@ffff4c00 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xffff4c00 0xb400>;
|
|
};
|
|
};
|
|
};
|