b3a5af435a
This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - Cleanups for Renesas shmobile platforms - Lots of added devices on LPC18xx - Lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5OMWAAoJEIwa5zzehBx3r2QP/1skn0zzgfvbK0kkPOh9q3Jk jX1elN4Wde1SnScz8UbdVb9nmdbhxsuYE/3+Lz7yCndWScBiak4qcsNHrSRhh3FA ST7Ub8DLc2TxY9K7eDkyVCcNkP35+UQTHCN76R5Lgrlfw3UO9Zr3xPFX3+Kd6aWz 9X8UnvJacQQIN/vO6J02kB96sKPEIANfuMgO6vDSbmcZ1RrdlHzjoRwAV0smECtJ NyOh+NQdPBR0gSl/peyKzAXoDHNXpDotltTmIz3tPA+dYBO/qG//B73H/oqox0ql AKAktyaDzdxXEuixPtAroo4dDy3xuIQ6xU+DNhPWQq0BgaxHWqkwq60d74ot8vCz 8gvC8pwA6gavbqVFNePOnwPNSyWZX01scX4fp903NjVM8/rGPvCR4y6p8lFIyVkG P0L8rmY/UYq3fieaAb1W0odASDrQpgg3zsHD7to43hz6jaRnMRCpA8nTVqJcyHqI E6YfGQH87Kpbvkjo0FYqo5P6xCCRTq+QUys6JruNYg05R/gd8AG7cXaVNO3yvg3T lRwNXDBt/zcp2exKnGR0IdGMUMICzsuoB8ZePkQdIWwePrd4AzT5qYJe/txmg1rd q+9VJqQkeF+txLd9XUV2W/Hcuzu3ZPCbs97I9tTKQHMGwKUZaPfuk2r4+4K+Ps5a dYwdms39p6AIT43rK+m3 =D2Pm -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
513 lines
11 KiB
Plaintext
513 lines
11 KiB
Plaintext
/*
|
|
* Copyright 2013 Gateworks Corporation
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
/ {
|
|
/* these are used by bootloader for disabling nodes */
|
|
aliases {
|
|
ethernet1 = ð1;
|
|
led0 = &led0;
|
|
led1 = &led1;
|
|
led2 = &led2;
|
|
nand = &gpmi;
|
|
ssi0 = &ssi1;
|
|
usb0 = &usbh1;
|
|
usb1 = &usbotg;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttymxc1,115200";
|
|
};
|
|
|
|
backlight {
|
|
compatible = "pwm-backlight";
|
|
pwms = <&pwm4 0 5000000>;
|
|
brightness-levels = <0 4 8 16 32 64 128 255>;
|
|
default-brightness-level = <7>;
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gpio_leds>;
|
|
|
|
led0: user1 {
|
|
label = "user1";
|
|
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
|
|
default-state = "on";
|
|
linux,default-trigger = "heartbeat";
|
|
};
|
|
|
|
led1: user2 {
|
|
label = "user2";
|
|
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
|
|
default-state = "off";
|
|
};
|
|
|
|
led2: user3 {
|
|
label = "user3";
|
|
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
|
|
default-state = "off";
|
|
};
|
|
};
|
|
|
|
memory {
|
|
reg = <0x10000000 0x40000000>;
|
|
};
|
|
|
|
pps {
|
|
compatible = "pps-gpio";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pps>;
|
|
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
|
|
status = "okay";
|
|
};
|
|
|
|
regulators {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg_1p0v: regulator@0 {
|
|
compatible = "regulator-fixed";
|
|
reg = <0>;
|
|
regulator-name = "1P0V";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* remove when pmic 1p8 regulator available */
|
|
reg_1p8v: regulator@1 {
|
|
compatible = "regulator-fixed";
|
|
reg = <1>;
|
|
regulator-name = "1P8V";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
reg_3p3v: regulator@2 {
|
|
compatible = "regulator-fixed";
|
|
reg = <2>;
|
|
regulator-name = "3P3V";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
reg_usb_h1_vbus: regulator@3 {
|
|
compatible = "regulator-fixed";
|
|
reg = <3>;
|
|
regulator-name = "usb_h1_vbus";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
reg_usb_otg_vbus: regulator@4 {
|
|
compatible = "regulator-fixed";
|
|
reg = <4>;
|
|
regulator-name = "usb_otg_vbus";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
};
|
|
|
|
sound {
|
|
compatible = "fsl,imx6q-ventana-sgtl5000",
|
|
"fsl,imx-audio-sgtl5000";
|
|
model = "sgtl5000-audio";
|
|
ssi-controller = <&ssi1>;
|
|
audio-codec = <&codec>;
|
|
audio-routing =
|
|
"MIC_IN", "Mic Jack",
|
|
"Mic Jack", "Mic Bias",
|
|
"Headphone Jack", "HP_OUT";
|
|
mux-int-port = <1>;
|
|
mux-ext-port = <4>;
|
|
};
|
|
};
|
|
|
|
&audmux {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_audmux>;
|
|
status = "okay";
|
|
};
|
|
|
|
&can1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_flexcan1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&fec {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_enet>;
|
|
phy-mode = "rgmii";
|
|
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmi {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gpmi_nand>;
|
|
status = "okay";
|
|
};
|
|
|
|
&hdmi {
|
|
ddc-i2c-bus = <&i2c3>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c1 {
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
status = "okay";
|
|
|
|
eeprom1: eeprom@50 {
|
|
compatible = "atmel,24c02";
|
|
reg = <0x50>;
|
|
pagesize = <16>;
|
|
};
|
|
|
|
eeprom2: eeprom@51 {
|
|
compatible = "atmel,24c02";
|
|
reg = <0x51>;
|
|
pagesize = <16>;
|
|
};
|
|
|
|
eeprom3: eeprom@52 {
|
|
compatible = "atmel,24c02";
|
|
reg = <0x52>;
|
|
pagesize = <16>;
|
|
};
|
|
|
|
eeprom4: eeprom@53 {
|
|
compatible = "atmel,24c02";
|
|
reg = <0x53>;
|
|
pagesize = <16>;
|
|
};
|
|
|
|
gpio: pca9555@23 {
|
|
compatible = "nxp,pca9555";
|
|
reg = <0x23>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
rtc: ds1672@68 {
|
|
compatible = "dallas,ds1672";
|
|
reg = <0x68>;
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c3 {
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
status = "okay";
|
|
|
|
codec: sgtl5000@0a {
|
|
compatible = "fsl,sgtl5000";
|
|
reg = <0x0a>;
|
|
clocks = <&clks 201>;
|
|
VDDA-supply = <®_1p8v>;
|
|
VDDIO-supply = <®_3p3v>;
|
|
};
|
|
|
|
touchscreen: egalax_ts@04 {
|
|
compatible = "eeti,egalax_ts";
|
|
reg = <0x04>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <11 2>;
|
|
wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
&ldb {
|
|
status = "okay";
|
|
|
|
lvds-channel@1 {
|
|
fsl,data-mapping = "spwg";
|
|
fsl,data-width = <18>;
|
|
status = "okay";
|
|
|
|
display-timings {
|
|
native-mode = <&timing0>;
|
|
timing0: hsd100pxn1 {
|
|
clock-frequency = <65000000>;
|
|
hactive = <1024>;
|
|
vactive = <768>;
|
|
hback-porch = <220>;
|
|
hfront-porch = <40>;
|
|
vback-porch = <21>;
|
|
vfront-porch = <7>;
|
|
hsync-len = <60>;
|
|
vsync-len = <10>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pcie {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcie>;
|
|
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
|
|
eth1: sky2@8 { /* MAC/PHY on bus 8 */
|
|
compatible = "marvell,sky2";
|
|
};
|
|
};
|
|
|
|
&pwm4 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm4>;
|
|
status = "okay";
|
|
};
|
|
|
|
&ssi1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart5 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart5>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg {
|
|
vbus-supply = <®_usb_otg_vbus>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usbotg>;
|
|
disable-over-current;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbh1 {
|
|
vbus-supply = <®_usb_h1_vbus>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
|
vmmc-supply = <®_3p3v>;
|
|
no-1-8-v; /* firmware will remove if board revision supports */
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
imx6qdl-gw53xx {
|
|
pinctrl_audmux: audmuxgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
|
|
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
|
|
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
|
|
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
|
|
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet: enetgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
|
|
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
|
|
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_leds: gpioledsgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
|
|
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
|
|
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
|
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
|
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
|
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
|
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
|
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
|
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
|
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
|
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
|
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
|
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
|
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
|
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
|
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
|
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
|
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
|
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcie: pciegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
|
|
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
|
|
>;
|
|
};
|
|
|
|
pinctrl_pps: ppsgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm4: pwm4grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5: uart5grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
|
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
|
|
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
|
|
>;
|
|
};
|
|
};
|
|
};
|