c09d0f7ce0
Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
56 lines
1.1 KiB
Plaintext
56 lines
1.1 KiB
Plaintext
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "skeleton.dtsi"
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#include "vfxxx.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a5_cpu: cpu@0 {
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compatible = "arm,cortex-a5";
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device_type = "cpu";
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reg = <0x0>;
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};
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};
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soc {
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aips-bus@40000000 {
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intc: interrupt-controller@40002000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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reg = <0x40003000 0x1000>,
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<0x40002100 0x100>;
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};
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global_timer: timer@40002200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x40002200 0x20>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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clocks = <&clks VF610_CLK_PLATFORM_BUS>;
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};
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};
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};
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};
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&mscm_ir {
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interrupt-parent = <&intc>;
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};
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&wdoga5 {
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status = "okay";
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};
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