5694cecdb0
In the end, we ended up with quite a lot more than I expected: - Support for ARMv8.3 Pointer Authentication in userspace (CRIU and kernel-side support to come later) - Support for per-thread stack canaries, pending an update to GCC that is currently undergoing review - Support for kexec_file_load(), which permits secure boot of a kexec payload but also happens to improve the performance of kexec dramatically because we can avoid the sucky purgatory code from userspace. Kdump will come later (requires updates to libfdt). - Optimisation of our dynamic CPU feature framework, so that all detected features are enabled via a single stop_machine() invocation - KPTI whitelisting of Cortex-A CPUs unaffected by Meltdown, so that they can benefit from global TLB entries when KASLR is not in use - 52-bit virtual addressing for userspace (kernel remains 48-bit) - Patch in LSE atomics for per-cpu atomic operations - Custom preempt.h implementation to avoid unconditional calls to preempt_schedule() from preempt_enable() - Support for the new 'SB' Speculation Barrier instruction - Vectorised implementation of XOR checksumming and CRC32 optimisations - Workaround for Cortex-A76 erratum #1165522 - Improved compatibility with Clang/LLD - Support for TX2 system PMUS for profiling the L3 cache and DMC - Reflect read-only permissions in the linear map by default - Ensure MMIO reads are ordered with subsequent calls to Xdelay() - Initial support for memory hotplug - Tweak the threshold when we invalidate the TLB by-ASID, so that mremap() performance is improved for ranges spanning multiple PMDs. - Minor refactoring and cleanups -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJcE4TmAAoJELescNyEwWM0Nr0H/iaU7/wQSzHyNXtZoImyKTul Blu2ga4/EqUrTU7AVVfmkl/3NBILWlgQVpY6tH6EfXQuvnxqD7CizbHyLdyO+z0S B5PsFUH2GLMNAi48AUNqGqkgb2knFbg+T+9IimijDBkKg1G/KhQnRg6bXX32mLJv Une8oshUPBVJMsHN1AcQknzKariuoE3u0SgJ+eOZ9yA2ZwKxP4yy1SkDt3xQrtI0 lojeRjxcyjTP1oGRNZC+BWUtGOT35p7y6cGTnBd/4TlqBGz5wVAJUcdoxnZ6JYVR O8+ob9zU+4I0+SKt80s7pTLqQiL9rxkKZ5joWK1pr1g9e0s5N5yoETXKFHgJYP8= =sYdt -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 festive updates from Will Deacon: "In the end, we ended up with quite a lot more than I expected: - Support for ARMv8.3 Pointer Authentication in userspace (CRIU and kernel-side support to come later) - Support for per-thread stack canaries, pending an update to GCC that is currently undergoing review - Support for kexec_file_load(), which permits secure boot of a kexec payload but also happens to improve the performance of kexec dramatically because we can avoid the sucky purgatory code from userspace. Kdump will come later (requires updates to libfdt). - Optimisation of our dynamic CPU feature framework, so that all detected features are enabled via a single stop_machine() invocation - KPTI whitelisting of Cortex-A CPUs unaffected by Meltdown, so that they can benefit from global TLB entries when KASLR is not in use - 52-bit virtual addressing for userspace (kernel remains 48-bit) - Patch in LSE atomics for per-cpu atomic operations - Custom preempt.h implementation to avoid unconditional calls to preempt_schedule() from preempt_enable() - Support for the new 'SB' Speculation Barrier instruction - Vectorised implementation of XOR checksumming and CRC32 optimisations - Workaround for Cortex-A76 erratum #1165522 - Improved compatibility with Clang/LLD - Support for TX2 system PMUS for profiling the L3 cache and DMC - Reflect read-only permissions in the linear map by default - Ensure MMIO reads are ordered with subsequent calls to Xdelay() - Initial support for memory hotplug - Tweak the threshold when we invalidate the TLB by-ASID, so that mremap() performance is improved for ranges spanning multiple PMDs. - Minor refactoring and cleanups" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (125 commits) arm64: kaslr: print PHYS_OFFSET in dump_kernel_offset() arm64: sysreg: Use _BITUL() when defining register bits arm64: cpufeature: Rework ptr auth hwcaps using multi_entry_cap_matches arm64: cpufeature: Reduce number of pointer auth CPU caps from 6 to 4 arm64: docs: document pointer authentication arm64: ptr auth: Move per-thread keys from thread_info to thread_struct arm64: enable pointer authentication arm64: add prctl control for resetting ptrauth keys arm64: perf: strip PAC when unwinding userspace arm64: expose user PAC bit positions via ptrace arm64: add basic pointer authentication support arm64/cpufeature: detect pointer authentication arm64: Don't trap host pointer auth use to EL2 arm64/kvm: hide ptrauth from guests arm64/kvm: consistently handle host HCR_EL2 flags arm64: add pointer authentication register bits arm64: add comments about EC exception levels arm64: perf: Treat EXCLUDE_EL* bit definitions as unsigned arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field arm64: enable per-task stack canaries ...
83 lines
5.2 KiB
Plaintext
83 lines
5.2 KiB
Plaintext
Silicon Errata and Software Workarounds
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=======================================
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Author: Will Deacon <will.deacon@arm.com>
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Date : 27 November 2015
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It is an unfortunate fact of life that hardware is often produced with
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so-called "errata", which can cause it to deviate from the architecture
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under specific circumstances. For hardware produced by ARM, these
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errata are broadly classified into the following categories:
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Category A: A critical error without a viable workaround.
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Category B: A significant or critical error with an acceptable
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workaround.
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Category C: A minor error that is not expected to occur under normal
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operation.
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For more information, consult one of the "Software Developers Errata
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Notice" documents available on infocenter.arm.com (registration
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required).
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As far as Linux is concerned, Category B errata may require some special
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treatment in the operating system. For example, avoiding a particular
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sequence of code, or configuring the processor in a particular way. A
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less common situation may require similar actions in order to declassify
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a Category A erratum into a Category C erratum. These are collectively
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known as "software workarounds" and are only required in the minority of
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cases (e.g. those cases that both require a non-secure workaround *and*
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can be triggered by Linux).
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For software workarounds that may adversely impact systems unaffected by
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the erratum in question, a Kconfig entry is added under "Kernel
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Features" -> "ARM errata workarounds via the alternatives framework".
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These are enabled by default and patched in at runtime when an affected
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CPU is detected. For less-intrusive workarounds, a Kconfig option is not
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available and the code is structured (preferably with a comment) in such
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a way that the erratum will not be hit.
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This approach can make it slightly onerous to determine exactly which
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errata are worked around in an arbitrary kernel source tree, so this
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file acts as a registry of software workarounds in the Linux Kernel and
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will be updated when new workarounds are committed and backported to
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stable kernels.
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| Implementor | Component | Erratum ID | Kconfig |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
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| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
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| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
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| ARM | Cortex-A57 | #852523 | N/A |
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| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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| ARM | Cortex-A72 | #853709 | N/A |
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
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| ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 |
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| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
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| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
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| ARM | MMU-500 | #841119,#826419 | N/A |
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| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
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| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
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| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
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| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 |
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| Cavium | ThunderX SMMUv2 | #27704 | N/A |
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| Cavium | ThunderX2 SMMUv3| #74 | N/A |
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| Cavium | ThunderX2 SMMUv3| #126 | N/A |
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| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
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| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
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| Hisilicon | Hip0{6,7} | #161010701 | N/A |
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| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
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| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
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| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
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| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
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| Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 |
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