![Marc Zyngier](/assets/img/avatar_default.png)
The ARM GIC interrupt controller offers per CPU interrupts (PPIs), which are usually used to connect local timers to each core. Each CPU has its own private interface to the GIC, and only sees the PPIs that are directly connect to it. While these timers are separate devices and have a separate interrupt line to a core, they all use the same IRQ number. For these devices, request_irq() is not the right API as it assumes that an IRQ number is visible by a number of CPUs (through the affinity setting), but makes it very awkward to express that an IRQ number can be handled by all CPUs, and yet be a different interrupt line on each CPU, requiring a different dev_id cookie to be passed back to the handler. The *_percpu_irq() functions is designed to overcome these limitations, by providing a per-cpu dev_id vector: int request_percpu_irq(unsigned int irq, irq_handler_t handler, const char *devname, void __percpu *percpu_dev_id); void free_percpu_irq(unsigned int, void __percpu *); int setup_percpu_irq(unsigned int irq, struct irqaction *new); void remove_percpu_irq(unsigned int irq, struct irqaction *act); void enable_percpu_irq(unsigned int irq); void disable_percpu_irq(unsigned int irq); The API has a number of limitations: - no interrupt sharing - no threading - common handler across all the CPUs Once the interrupt is requested using setup_percpu_irq() or request_percpu_irq(), it must be enabled by each core that wishes its local interrupt to be delivered. Based on an initial patch by Thomas Gleixner. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1316793788-14500-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
749 lines
22 KiB
C
749 lines
22 KiB
C
#ifndef _LINUX_IRQ_H
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#define _LINUX_IRQ_H
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/*
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* Please do not include this file in generic code. There is currently
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* no requirement for any architecture to implement anything held
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* within this file.
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*
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* Thanks. --rmk
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*/
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#include <linux/smp.h>
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#ifndef CONFIG_S390
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#include <linux/linkage.h>
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#include <linux/cache.h>
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#include <linux/spinlock.h>
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#include <linux/cpumask.h>
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#include <linux/gfp.h>
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#include <linux/irqreturn.h>
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#include <linux/irqnr.h>
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#include <linux/errno.h>
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#include <linux/topology.h>
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#include <linux/wait.h>
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#include <linux/module.h>
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#include <asm/irq.h>
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#include <asm/ptrace.h>
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#include <asm/irq_regs.h>
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struct seq_file;
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struct irq_desc;
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struct irq_data;
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typedef void (*irq_flow_handler_t)(unsigned int irq,
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struct irq_desc *desc);
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typedef void (*irq_preflow_handler_t)(struct irq_data *data);
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/*
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* IRQ line status.
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*
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* Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
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*
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* IRQ_TYPE_NONE - default, unspecified type
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* IRQ_TYPE_EDGE_RISING - rising edge triggered
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* IRQ_TYPE_EDGE_FALLING - falling edge triggered
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* IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
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* IRQ_TYPE_LEVEL_HIGH - high level triggered
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* IRQ_TYPE_LEVEL_LOW - low level triggered
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* IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
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* IRQ_TYPE_SENSE_MASK - Mask for all the above bits
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* IRQ_TYPE_PROBE - Special flag for probing in progress
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*
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* Bits which can be modified via irq_set/clear/modify_status_flags()
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* IRQ_LEVEL - Interrupt is level type. Will be also
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* updated in the code when the above trigger
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* bits are modified via irq_set_irq_type()
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* IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
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* it from affinity setting
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* IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
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* IRQ_NOREQUEST - Interrupt cannot be requested via
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* request_irq()
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* IRQ_NOTHREAD - Interrupt cannot be threaded
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* IRQ_NOAUTOEN - Interrupt is not automatically enabled in
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* request/setup_irq()
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* IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
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* IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
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* IRQ_NESTED_TRHEAD - Interrupt nests into another thread
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* IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
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*/
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enum {
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IRQ_TYPE_NONE = 0x00000000,
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IRQ_TYPE_EDGE_RISING = 0x00000001,
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IRQ_TYPE_EDGE_FALLING = 0x00000002,
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IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
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IRQ_TYPE_LEVEL_HIGH = 0x00000004,
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IRQ_TYPE_LEVEL_LOW = 0x00000008,
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IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
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IRQ_TYPE_SENSE_MASK = 0x0000000f,
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IRQ_TYPE_PROBE = 0x00000010,
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IRQ_LEVEL = (1 << 8),
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IRQ_PER_CPU = (1 << 9),
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IRQ_NOPROBE = (1 << 10),
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IRQ_NOREQUEST = (1 << 11),
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IRQ_NOAUTOEN = (1 << 12),
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IRQ_NO_BALANCING = (1 << 13),
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IRQ_MOVE_PCNTXT = (1 << 14),
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IRQ_NESTED_THREAD = (1 << 15),
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IRQ_NOTHREAD = (1 << 16),
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IRQ_PER_CPU_DEVID = (1 << 17),
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};
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#define IRQF_MODIFY_MASK \
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(IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
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IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
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IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID)
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#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
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/*
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* Return value for chip->irq_set_affinity()
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*
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* IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
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* IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
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*/
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enum {
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IRQ_SET_MASK_OK = 0,
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IRQ_SET_MASK_OK_NOCOPY,
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};
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struct msi_desc;
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struct irq_domain;
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/**
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* struct irq_data - per irq and irq chip data passed down to chip functions
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* @irq: interrupt number
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* @hwirq: hardware interrupt number, local to the interrupt domain
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* @node: node index useful for balancing
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* @state_use_accessors: status information for irq chip functions.
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* Use accessor functions to deal with it
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* @chip: low level interrupt hardware access
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* @domain: Interrupt translation domain; responsible for mapping
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* between hwirq number and linux irq number.
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* @handler_data: per-IRQ data for the irq_chip methods
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* @chip_data: platform-specific per-chip private data for the chip
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* methods, to allow shared chip implementations
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* @msi_desc: MSI descriptor
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* @affinity: IRQ affinity on SMP
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*
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* The fields here need to overlay the ones in irq_desc until we
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* cleaned up the direct references and switched everything over to
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* irq_data.
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*/
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struct irq_data {
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unsigned int irq;
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unsigned long hwirq;
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unsigned int node;
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unsigned int state_use_accessors;
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struct irq_chip *chip;
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struct irq_domain *domain;
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void *handler_data;
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void *chip_data;
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struct msi_desc *msi_desc;
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#ifdef CONFIG_SMP
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cpumask_var_t affinity;
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#endif
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};
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/*
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* Bit masks for irq_data.state
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*
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* IRQD_TRIGGER_MASK - Mask for the trigger type bits
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* IRQD_SETAFFINITY_PENDING - Affinity setting is pending
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* IRQD_NO_BALANCING - Balancing disabled for this IRQ
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* IRQD_PER_CPU - Interrupt is per cpu
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* IRQD_AFFINITY_SET - Interrupt affinity was set
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* IRQD_LEVEL - Interrupt is level triggered
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* IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
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* from suspend
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* IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
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* context
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* IRQD_IRQ_DISABLED - Disabled state of the interrupt
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* IRQD_IRQ_MASKED - Masked state of the interrupt
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* IRQD_IRQ_INPROGRESS - In progress state of the interrupt
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*/
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enum {
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IRQD_TRIGGER_MASK = 0xf,
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IRQD_SETAFFINITY_PENDING = (1 << 8),
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IRQD_NO_BALANCING = (1 << 10),
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IRQD_PER_CPU = (1 << 11),
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IRQD_AFFINITY_SET = (1 << 12),
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IRQD_LEVEL = (1 << 13),
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IRQD_WAKEUP_STATE = (1 << 14),
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IRQD_MOVE_PCNTXT = (1 << 15),
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IRQD_IRQ_DISABLED = (1 << 16),
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IRQD_IRQ_MASKED = (1 << 17),
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IRQD_IRQ_INPROGRESS = (1 << 18),
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};
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static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
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}
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static inline bool irqd_is_per_cpu(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_PER_CPU;
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}
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static inline bool irqd_can_balance(struct irq_data *d)
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{
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return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
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}
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static inline bool irqd_affinity_was_set(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_AFFINITY_SET;
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}
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static inline void irqd_mark_affinity_was_set(struct irq_data *d)
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{
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d->state_use_accessors |= IRQD_AFFINITY_SET;
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}
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static inline u32 irqd_get_trigger_type(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_TRIGGER_MASK;
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}
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/*
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* Must only be called inside irq_chip.irq_set_type() functions.
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*/
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static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
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{
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d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
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d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
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}
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static inline bool irqd_is_level_type(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_LEVEL;
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}
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static inline bool irqd_is_wakeup_set(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_WAKEUP_STATE;
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}
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static inline bool irqd_can_move_in_process_context(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_MOVE_PCNTXT;
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}
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static inline bool irqd_irq_disabled(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_IRQ_DISABLED;
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}
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static inline bool irqd_irq_masked(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_IRQ_MASKED;
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}
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static inline bool irqd_irq_inprogress(struct irq_data *d)
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{
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return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
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}
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/*
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* Functions for chained handlers which can be enabled/disabled by the
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* standard disable_irq/enable_irq calls. Must be called with
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* irq_desc->lock held.
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*/
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static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
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{
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d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
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}
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static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
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{
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d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
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}
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/**
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* struct irq_chip - hardware interrupt chip descriptor
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*
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* @name: name for /proc/interrupts
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* @irq_startup: start up the interrupt (defaults to ->enable if NULL)
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* @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
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* @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
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* @irq_disable: disable the interrupt
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* @irq_ack: start of a new interrupt
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* @irq_mask: mask an interrupt source
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* @irq_mask_ack: ack and mask an interrupt source
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* @irq_unmask: unmask an interrupt source
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* @irq_eoi: end of interrupt
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* @irq_set_affinity: set the CPU affinity on SMP machines
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* @irq_retrigger: resend an IRQ to the CPU
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* @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
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* @irq_set_wake: enable/disable power-management wake-on of an IRQ
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* @irq_bus_lock: function to lock access to slow bus (i2c) chips
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* @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
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* @irq_cpu_online: configure an interrupt source for a secondary CPU
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* @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
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* @irq_suspend: function called from core code on suspend once per chip
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* @irq_resume: function called from core code on resume once per chip
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* @irq_pm_shutdown: function called from core code on shutdown once per chip
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* @irq_print_chip: optional to print special chip info in show_interrupts
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* @flags: chip specific flags
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*
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* @release: release function solely used by UML
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*/
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struct irq_chip {
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const char *name;
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unsigned int (*irq_startup)(struct irq_data *data);
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void (*irq_shutdown)(struct irq_data *data);
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void (*irq_enable)(struct irq_data *data);
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void (*irq_disable)(struct irq_data *data);
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void (*irq_ack)(struct irq_data *data);
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void (*irq_mask)(struct irq_data *data);
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void (*irq_mask_ack)(struct irq_data *data);
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void (*irq_unmask)(struct irq_data *data);
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void (*irq_eoi)(struct irq_data *data);
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int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
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int (*irq_retrigger)(struct irq_data *data);
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int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
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int (*irq_set_wake)(struct irq_data *data, unsigned int on);
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void (*irq_bus_lock)(struct irq_data *data);
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void (*irq_bus_sync_unlock)(struct irq_data *data);
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void (*irq_cpu_online)(struct irq_data *data);
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void (*irq_cpu_offline)(struct irq_data *data);
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void (*irq_suspend)(struct irq_data *data);
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void (*irq_resume)(struct irq_data *data);
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void (*irq_pm_shutdown)(struct irq_data *data);
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void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
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unsigned long flags;
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/* Currently used only by UML, might disappear one day.*/
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#ifdef CONFIG_IRQ_RELEASE_METHOD
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void (*release)(unsigned int irq, void *dev_id);
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#endif
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};
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/*
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* irq_chip specific flags
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*
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* IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
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* IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
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* IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
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* IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
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* when irq enabled
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* IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
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*/
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enum {
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IRQCHIP_SET_TYPE_MASKED = (1 << 0),
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IRQCHIP_EOI_IF_HANDLED = (1 << 1),
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IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
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IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
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IRQCHIP_SKIP_SET_WAKE = (1 << 4),
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};
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/* This include will go away once we isolated irq_desc usage to core code */
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#include <linux/irqdesc.h>
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/*
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* Pick up the arch-dependent methods:
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*/
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#include <asm/hw_irq.h>
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#ifndef NR_IRQS_LEGACY
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# define NR_IRQS_LEGACY 0
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#endif
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#ifndef ARCH_IRQ_INIT_FLAGS
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# define ARCH_IRQ_INIT_FLAGS 0
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#endif
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#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
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struct irqaction;
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extern int setup_irq(unsigned int irq, struct irqaction *new);
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extern void remove_irq(unsigned int irq, struct irqaction *act);
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extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
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extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
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extern void irq_cpu_online(void);
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extern void irq_cpu_offline(void);
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extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask);
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#ifdef CONFIG_GENERIC_HARDIRQS
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#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
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void irq_move_irq(struct irq_data *data);
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void irq_move_masked_irq(struct irq_data *data);
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#else
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static inline void irq_move_irq(struct irq_data *data) { }
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static inline void irq_move_masked_irq(struct irq_data *data) { }
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#endif
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extern int no_irq_affinity;
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/*
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* Built-in IRQ handlers for various IRQ types,
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* callable via desc->handle_irq()
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*/
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extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
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extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
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extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
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extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
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extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
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extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
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extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
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extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
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extern void handle_nested_irq(unsigned int irq);
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/* Handling of unhandled and spurious interrupts: */
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extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
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irqreturn_t action_ret);
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/* Enable/disable irq debugging output: */
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extern int noirqdebug_setup(char *str);
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/* Checks whether the interrupt can be requested by request_irq(): */
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extern int can_request_irq(unsigned int irq, unsigned long irqflags);
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/* Dummy irq-chip implementations: */
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extern struct irq_chip no_irq_chip;
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extern struct irq_chip dummy_irq_chip;
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extern void
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irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
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irq_flow_handler_t handle, const char *name);
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static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
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irq_flow_handler_t handle)
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{
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irq_set_chip_and_handler_name(irq, chip, handle, NULL);
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}
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extern int irq_set_percpu_devid(unsigned int irq);
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|
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extern void
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__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
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const char *name);
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static inline void
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irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
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{
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__irq_set_handler(irq, handle, 0, NULL);
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}
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/*
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* Set a highlevel chained flow handler for a given IRQ.
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* (a chained handler is automatically enabled and set to
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* IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
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*/
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static inline void
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irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
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{
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__irq_set_handler(irq, handle, 1, NULL);
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}
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void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
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static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
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{
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irq_modify_status(irq, 0, set);
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}
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static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
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{
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irq_modify_status(irq, clr, 0);
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}
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static inline void irq_set_noprobe(unsigned int irq)
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{
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irq_modify_status(irq, 0, IRQ_NOPROBE);
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}
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static inline void irq_set_probe(unsigned int irq)
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{
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irq_modify_status(irq, IRQ_NOPROBE, 0);
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}
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static inline void irq_set_nothread(unsigned int irq)
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{
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irq_modify_status(irq, 0, IRQ_NOTHREAD);
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}
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static inline void irq_set_thread(unsigned int irq)
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{
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irq_modify_status(irq, IRQ_NOTHREAD, 0);
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}
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static inline void irq_set_nested_thread(unsigned int irq, bool nest)
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|
{
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if (nest)
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irq_set_status_flags(irq, IRQ_NESTED_THREAD);
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else
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irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
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}
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static inline void irq_set_percpu_devid_flags(unsigned int irq)
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|
{
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irq_set_status_flags(irq,
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IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
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IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
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}
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/* Handle dynamic irq creation and destruction */
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extern unsigned int create_irq_nr(unsigned int irq_want, int node);
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extern int create_irq(void);
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extern void destroy_irq(unsigned int irq);
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|
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/*
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* Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and
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* irq_free_desc instead.
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*/
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extern void dynamic_irq_cleanup(unsigned int irq);
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static inline void dynamic_irq_init(unsigned int irq)
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|
{
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dynamic_irq_cleanup(irq);
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}
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|
|
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/* Set/get chip/data for an IRQ: */
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extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
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extern int irq_set_handler_data(unsigned int irq, void *data);
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extern int irq_set_chip_data(unsigned int irq, void *data);
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extern int irq_set_irq_type(unsigned int irq, unsigned int type);
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extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
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extern struct irq_data *irq_get_irq_data(unsigned int irq);
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|
|
|
static inline struct irq_chip *irq_get_chip(unsigned int irq)
|
|
{
|
|
struct irq_data *d = irq_get_irq_data(irq);
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|
return d ? d->chip : NULL;
|
|
}
|
|
|
|
static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
|
|
{
|
|
return d->chip;
|
|
}
|
|
|
|
static inline void *irq_get_chip_data(unsigned int irq)
|
|
{
|
|
struct irq_data *d = irq_get_irq_data(irq);
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|
return d ? d->chip_data : NULL;
|
|
}
|
|
|
|
static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
|
|
{
|
|
return d->chip_data;
|
|
}
|
|
|
|
static inline void *irq_get_handler_data(unsigned int irq)
|
|
{
|
|
struct irq_data *d = irq_get_irq_data(irq);
|
|
return d ? d->handler_data : NULL;
|
|
}
|
|
|
|
static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
|
|
{
|
|
return d->handler_data;
|
|
}
|
|
|
|
static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
|
|
{
|
|
struct irq_data *d = irq_get_irq_data(irq);
|
|
return d ? d->msi_desc : NULL;
|
|
}
|
|
|
|
static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
|
|
{
|
|
return d->msi_desc;
|
|
}
|
|
|
|
int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
|
|
struct module *owner);
|
|
|
|
static inline int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt,
|
|
int node)
|
|
{
|
|
return __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE);
|
|
}
|
|
|
|
void irq_free_descs(unsigned int irq, unsigned int cnt);
|
|
int irq_reserve_irqs(unsigned int from, unsigned int cnt);
|
|
|
|
static inline int irq_alloc_desc(int node)
|
|
{
|
|
return irq_alloc_descs(-1, 0, 1, node);
|
|
}
|
|
|
|
static inline int irq_alloc_desc_at(unsigned int at, int node)
|
|
{
|
|
return irq_alloc_descs(at, at, 1, node);
|
|
}
|
|
|
|
static inline int irq_alloc_desc_from(unsigned int from, int node)
|
|
{
|
|
return irq_alloc_descs(-1, from, 1, node);
|
|
}
|
|
|
|
static inline void irq_free_desc(unsigned int irq)
|
|
{
|
|
irq_free_descs(irq, 1);
|
|
}
|
|
|
|
static inline int irq_reserve_irq(unsigned int irq)
|
|
{
|
|
return irq_reserve_irqs(irq, 1);
|
|
}
|
|
|
|
#ifndef irq_reg_writel
|
|
# define irq_reg_writel(val, addr) writel(val, addr)
|
|
#endif
|
|
#ifndef irq_reg_readl
|
|
# define irq_reg_readl(addr) readl(addr)
|
|
#endif
|
|
|
|
/**
|
|
* struct irq_chip_regs - register offsets for struct irq_gci
|
|
* @enable: Enable register offset to reg_base
|
|
* @disable: Disable register offset to reg_base
|
|
* @mask: Mask register offset to reg_base
|
|
* @ack: Ack register offset to reg_base
|
|
* @eoi: Eoi register offset to reg_base
|
|
* @type: Type configuration register offset to reg_base
|
|
* @polarity: Polarity configuration register offset to reg_base
|
|
*/
|
|
struct irq_chip_regs {
|
|
unsigned long enable;
|
|
unsigned long disable;
|
|
unsigned long mask;
|
|
unsigned long ack;
|
|
unsigned long eoi;
|
|
unsigned long type;
|
|
unsigned long polarity;
|
|
};
|
|
|
|
/**
|
|
* struct irq_chip_type - Generic interrupt chip instance for a flow type
|
|
* @chip: The real interrupt chip which provides the callbacks
|
|
* @regs: Register offsets for this chip
|
|
* @handler: Flow handler associated with this chip
|
|
* @type: Chip can handle these flow types
|
|
*
|
|
* A irq_generic_chip can have several instances of irq_chip_type when
|
|
* it requires different functions and register offsets for different
|
|
* flow types.
|
|
*/
|
|
struct irq_chip_type {
|
|
struct irq_chip chip;
|
|
struct irq_chip_regs regs;
|
|
irq_flow_handler_t handler;
|
|
u32 type;
|
|
};
|
|
|
|
/**
|
|
* struct irq_chip_generic - Generic irq chip data structure
|
|
* @lock: Lock to protect register and cache data access
|
|
* @reg_base: Register base address (virtual)
|
|
* @irq_base: Interrupt base nr for this chip
|
|
* @irq_cnt: Number of interrupts handled by this chip
|
|
* @mask_cache: Cached mask register
|
|
* @type_cache: Cached type register
|
|
* @polarity_cache: Cached polarity register
|
|
* @wake_enabled: Interrupt can wakeup from suspend
|
|
* @wake_active: Interrupt is marked as an wakeup from suspend source
|
|
* @num_ct: Number of available irq_chip_type instances (usually 1)
|
|
* @private: Private data for non generic chip callbacks
|
|
* @list: List head for keeping track of instances
|
|
* @chip_types: Array of interrupt irq_chip_types
|
|
*
|
|
* Note, that irq_chip_generic can have multiple irq_chip_type
|
|
* implementations which can be associated to a particular irq line of
|
|
* an irq_chip_generic instance. That allows to share and protect
|
|
* state in an irq_chip_generic instance when we need to implement
|
|
* different flow mechanisms (level/edge) for it.
|
|
*/
|
|
struct irq_chip_generic {
|
|
raw_spinlock_t lock;
|
|
void __iomem *reg_base;
|
|
unsigned int irq_base;
|
|
unsigned int irq_cnt;
|
|
u32 mask_cache;
|
|
u32 type_cache;
|
|
u32 polarity_cache;
|
|
u32 wake_enabled;
|
|
u32 wake_active;
|
|
unsigned int num_ct;
|
|
void *private;
|
|
struct list_head list;
|
|
struct irq_chip_type chip_types[0];
|
|
};
|
|
|
|
/**
|
|
* enum irq_gc_flags - Initialization flags for generic irq chips
|
|
* @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
|
|
* @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
|
|
* irq chips which need to call irq_set_wake() on
|
|
* the parent irq. Usually GPIO implementations
|
|
*/
|
|
enum irq_gc_flags {
|
|
IRQ_GC_INIT_MASK_CACHE = 1 << 0,
|
|
IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
|
|
};
|
|
|
|
/* Generic chip callback functions */
|
|
void irq_gc_noop(struct irq_data *d);
|
|
void irq_gc_mask_disable_reg(struct irq_data *d);
|
|
void irq_gc_mask_set_bit(struct irq_data *d);
|
|
void irq_gc_mask_clr_bit(struct irq_data *d);
|
|
void irq_gc_unmask_enable_reg(struct irq_data *d);
|
|
void irq_gc_ack_set_bit(struct irq_data *d);
|
|
void irq_gc_ack_clr_bit(struct irq_data *d);
|
|
void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
|
|
void irq_gc_eoi(struct irq_data *d);
|
|
int irq_gc_set_wake(struct irq_data *d, unsigned int on);
|
|
|
|
/* Setup functions for irq_chip_generic */
|
|
struct irq_chip_generic *
|
|
irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
|
|
void __iomem *reg_base, irq_flow_handler_t handler);
|
|
void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
|
|
enum irq_gc_flags flags, unsigned int clr,
|
|
unsigned int set);
|
|
int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
|
|
void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
|
|
unsigned int clr, unsigned int set);
|
|
|
|
static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
|
|
{
|
|
return container_of(d->chip, struct irq_chip_type, chip);
|
|
}
|
|
|
|
#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
|
|
|
|
#ifdef CONFIG_SMP
|
|
static inline void irq_gc_lock(struct irq_chip_generic *gc)
|
|
{
|
|
raw_spin_lock(&gc->lock);
|
|
}
|
|
|
|
static inline void irq_gc_unlock(struct irq_chip_generic *gc)
|
|
{
|
|
raw_spin_unlock(&gc->lock);
|
|
}
|
|
#else
|
|
static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
|
|
static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
|
|
#endif
|
|
|
|
#endif /* CONFIG_GENERIC_HARDIRQS */
|
|
|
|
#endif /* !CONFIG_S390 */
|
|
|
|
#endif /* _LINUX_IRQ_H */
|