494e5b6fae
sparc: Resolve conflict between sparc v9 and M7 on usage of bit 9 of TTE Bit 9 of TTE is CV (Cacheable in V-cache) on sparc v9 processor while the same bit 9 is MCDE (Memory Corruption Detection Enable) on M7 processor. This creates a conflicting usage of the same bit. Kernel sets TTE.cv bit on all pages for sun4v architecture which works well for sparc v9 but enables memory corruption detection on M7 processor which is not the intent. This patch adds code to determine if kernel is running on M7 processor and takes steps to not enable memory corruption detection in TTE erroneously. Signed-off-by: Khalid Aziz <khalid.aziz@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
158 lines
2.8 KiB
ArmAsm
158 lines
2.8 KiB
ArmAsm
/* ld script for sparc32/sparc64 kernel */
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#include <asm-generic/vmlinux.lds.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#ifdef CONFIG_SPARC32
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#define INITIAL_ADDRESS 0x10000 + SIZEOF_HEADERS
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#define TEXTSTART 0xf0004000
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#define SMP_CACHE_BYTES_SHIFT 5
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#else
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#define SMP_CACHE_BYTES_SHIFT 6
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#define INITIAL_ADDRESS 0x4000
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#define TEXTSTART 0x0000000000404000
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#endif
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#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
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#ifdef CONFIG_SPARC32
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OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
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OUTPUT_ARCH(sparc)
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ENTRY(_start)
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jiffies = jiffies_64 + 4;
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#else
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/* sparc64 */
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OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "elf64-sparc")
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OUTPUT_ARCH(sparc:v9a)
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ENTRY(_start)
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jiffies = jiffies_64;
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#endif
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SECTIONS
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{
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#ifdef CONFIG_SPARC64
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swapper_pg_dir = 0x0000000000402000;
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#endif
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. = INITIAL_ADDRESS;
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.text TEXTSTART :
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{
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_text = .;
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HEAD_TEXT
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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IRQENTRY_TEXT
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*(.gnu.warning)
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} = 0
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_etext = .;
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RO_DATA(PAGE_SIZE)
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/* Start of data section */
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_sdata = .;
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.data1 : {
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*(.data1)
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}
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RW_DATA_SECTION(SMP_CACHE_BYTES, 0, THREAD_SIZE)
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/* End of data section */
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_edata = .;
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.fixup : {
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__start___fixup = .;
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*(.fixup)
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__stop___fixup = .;
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}
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EXCEPTION_TABLE(16)
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NOTES
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. = ALIGN(PAGE_SIZE);
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__init_begin = ALIGN(PAGE_SIZE);
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INIT_TEXT_SECTION(PAGE_SIZE)
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__init_text_end = .;
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INIT_DATA_SECTION(16)
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. = ALIGN(4);
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.tsb_ldquad_phys_patch : {
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__tsb_ldquad_phys_patch = .;
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*(.tsb_ldquad_phys_patch)
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__tsb_ldquad_phys_patch_end = .;
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}
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.tsb_phys_patch : {
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__tsb_phys_patch = .;
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*(.tsb_phys_patch)
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__tsb_phys_patch_end = .;
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}
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.cpuid_patch : {
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__cpuid_patch = .;
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*(.cpuid_patch)
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__cpuid_patch_end = .;
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}
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.sun4v_1insn_patch : {
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__sun4v_1insn_patch = .;
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*(.sun4v_1insn_patch)
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__sun4v_1insn_patch_end = .;
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}
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.sun4v_2insn_patch : {
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__sun4v_2insn_patch = .;
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*(.sun4v_2insn_patch)
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__sun4v_2insn_patch_end = .;
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}
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.leon_1insn_patch : {
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__leon_1insn_patch = .;
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*(.leon_1insn_patch)
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__leon_1insn_patch_end = .;
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}
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.swapper_tsb_phys_patch : {
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__swapper_tsb_phys_patch = .;
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*(.swapper_tsb_phys_patch)
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__swapper_tsb_phys_patch_end = .;
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}
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.swapper_4m_tsb_phys_patch : {
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__swapper_4m_tsb_phys_patch = .;
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*(.swapper_4m_tsb_phys_patch)
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__swapper_4m_tsb_phys_patch_end = .;
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}
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.popc_3insn_patch : {
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__popc_3insn_patch = .;
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*(.popc_3insn_patch)
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__popc_3insn_patch_end = .;
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}
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.popc_6insn_patch : {
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__popc_6insn_patch = .;
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*(.popc_6insn_patch)
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__popc_6insn_patch_end = .;
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}
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.pause_3insn_patch : {
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__pause_3insn_patch = .;
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*(.pause_3insn_patch)
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__pause_3insn_patch_end = .;
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}
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.sun_m7_2insn_patch : {
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__sun_m7_2insn_patch = .;
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*(.sun_m7_2insn_patch)
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__sun_m7_2insn_patch_end = .;
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}
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PERCPU_SECTION(SMP_CACHE_BYTES)
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. = ALIGN(PAGE_SIZE);
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__init_end = .;
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BSS_SECTION(0, 0, 0)
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_end = . ;
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STABS_DEBUG
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DWARF_DEBUG
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DISCARDS
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}
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