bb71ad8802
Contention for scarce PCI memory resources has been growing due to an increasing number of PCI slots in large multi-node systems. The kernel currently attempts by default to allocate memory for all PCI expansion ROMs so there has also been an increasing number of PCI memory allocation failures seen on these systems. This occurs because the BIOS either (1) provides insufficient PCI memory resource for all the expansion ROMs or (2) provides adequate PCI memory resource for expansion ROMs but provides the space in kernel unexpected BIOS assigned P2P non-prefetch windows. The resulting PCI memory allocation failures may be benign when related to memory requests for expansion ROMs themselves but in some cases they can occur when attempting to allocate space for more critical BARs. This can happen when a successful expansion ROM allocation request consumes memory resource that was intended for a non-ROM BAR. We have seen this happen during PCI hotplug of an adapter that contains a P2P bridge where successful memory allocation for an expansion ROM BAR on device behind the bridge consumed memory that was intended for a non-ROM BAR on the P2P bridge. In all cases the allocation failure messages can be very confusing for users. This patch provides a new 'pci=norom' kernel boot parameter that can be used to disable the default PCI expansion ROM memory resource allocation. This provides a way to avoid the above described issues on systems that do not contain PCI devices for which drivers or user-level applications depend on the default PCI expansion ROM memory resource allocation behavior. Signed-off-by: Gary Hade <garyhade@us.ibm.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
154 lines
3.9 KiB
C
154 lines
3.9 KiB
C
/*
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* Low-Level PCI Access for i386 machines.
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*
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* (c) 1999 Martin Mares <mj@ucw.cz>
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*/
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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#define PCI_PROBE_BIOS 0x0001
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#define PCI_PROBE_CONF1 0x0002
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#define PCI_PROBE_CONF2 0x0004
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#define PCI_PROBE_MMCONF 0x0008
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#define PCI_PROBE_MASK 0x000f
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#define PCI_PROBE_NOEARLY 0x0010
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#define PCI_NO_CHECKS 0x0400
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#define PCI_USE_PIRQ_MASK 0x0800
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#define PCI_ASSIGN_ROMS 0x1000
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#define PCI_BIOS_IRQ_SCAN 0x2000
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#define PCI_ASSIGN_ALL_BUSSES 0x4000
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#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
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#define PCI_USE__CRS 0x10000
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#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
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#define PCI_NOASSIGN_ROMS 0x40000
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extern unsigned int pci_probe;
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extern unsigned long pirq_table_addr;
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enum pci_bf_sort_state {
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pci_bf_sort_default,
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pci_force_nobf,
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pci_force_bf,
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pci_dmi_bf,
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};
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extern void __init dmi_check_pciprobe(void);
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extern void __init dmi_check_skip_isa_align(void);
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/* pci-i386.c */
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extern unsigned int pcibios_max_latency;
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void pcibios_resource_survey(void);
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/* pci-pc.c */
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extern int pcibios_last_bus;
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extern struct pci_bus *pci_root_bus;
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extern struct pci_ops pci_root_ops;
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/* pci-irq.c */
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struct irq_info {
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u8 bus, devfn; /* Bus, device and function */
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struct {
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u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
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u16 bitmap; /* Available IRQs */
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} __attribute__((packed)) irq[4];
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u8 slot; /* Slot number, 0=onboard */
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u8 rfu;
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} __attribute__((packed));
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struct irq_routing_table {
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u32 signature; /* PIRQ_SIGNATURE should be here */
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u16 version; /* PIRQ_VERSION */
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u16 size; /* Table size in bytes */
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u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
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u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
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u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
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u32 miniport_data; /* Crap */
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u8 rfu[11];
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u8 checksum; /* Modulo 256 checksum must give zero */
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struct irq_info slots[0];
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} __attribute__((packed));
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extern unsigned int pcibios_irq_mask;
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extern int pcibios_scanned;
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extern spinlock_t pci_config_lock;
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extern int (*pcibios_enable_irq)(struct pci_dev *dev);
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extern void (*pcibios_disable_irq)(struct pci_dev *dev);
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struct pci_raw_ops {
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int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *val);
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int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 val);
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};
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extern struct pci_raw_ops *raw_pci_ops;
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extern struct pci_raw_ops *raw_pci_ext_ops;
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extern struct pci_raw_ops pci_direct_conf1;
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extern int pci_direct_probe(void);
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extern void pci_direct_init(int type);
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extern void pci_pcbios_init(void);
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extern int pci_olpc_init(void);
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/* pci-mmconfig.c */
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extern int __init pci_mmcfg_arch_init(void);
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extern void __init pci_mmcfg_arch_free(void);
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/*
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* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
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* on their northbrige except through the * %eax register. As such, you MUST
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* NOT use normal IOMEM accesses, you need to only use the magic mmio-config
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* accessor functions.
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* In fact just use pci_config_*, nothing else please.
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*/
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static inline unsigned char mmio_config_readb(void __iomem *pos)
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{
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u8 val;
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asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline unsigned short mmio_config_readw(void __iomem *pos)
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{
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u16 val;
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asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline unsigned int mmio_config_readl(void __iomem *pos)
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{
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u32 val;
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asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline void mmio_config_writeb(void __iomem *pos, u8 val)
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{
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asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
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}
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static inline void mmio_config_writew(void __iomem *pos, u16 val)
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{
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asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
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}
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static inline void mmio_config_writel(void __iomem *pos, u32 val)
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{
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asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
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}
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