1b3c5cdab4
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
275 lines
6.1 KiB
Plaintext
275 lines
6.1 KiB
Plaintext
/*
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* MPC8540 ADS Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8540ADS";
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compatible = "MPC8540ADS", "MPC85xxADS";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8540@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>; // 33 MHz, from uboot
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bus-frequency = <0>; // 166 MHz
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clock-frequency = <0>; // 825 MHz, from uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 08000000>; // 128M at 0x0
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};
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soc8540@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00100000>; // CCSRBAR 1M
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bus-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,8540-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <12 2>;
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};
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l2-cache-controller@20000 {
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compatible = "fsl,8540-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <10 2>;
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};
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "mdio";
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compatible = "gianfar";
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reg = <24520 20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <7 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <24000 1000>;
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/*
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* address is deprecated and will be removed
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* in 2.6.25. Only recent versions of
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* U-Boot support local-mac-address, however.
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*/
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address = [ 00 00 00 00 00 00 ];
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1d 2 1e 2 22 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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};
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ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <25000 1000>;
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/*
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* address is deprecated and will be removed
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* in 2.6.25. Only recent versions of
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* U-Boot support local-mac-address, however.
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*/
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address = [ 00 00 00 00 00 00 ];
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <23 2 24 2 28 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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};
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ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "FEC";
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compatible = "gianfar";
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reg = <26000 1000>;
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/*
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* address is deprecated and will be removed
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* in 2.6.25. Only recent versions of
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* U-Boot support local-mac-address, however.
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*/
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address = [ 00 00 00 00 00 00 ];
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy3>;
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};
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <40000 40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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};
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pci@e0008000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x02 */
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1000 0 0 1 &mpic 1 1
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1000 0 0 2 &mpic 2 1
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1000 0 0 3 &mpic 3 1
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1000 0 0 4 &mpic 4 1
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/* IDSEL 0x03 */
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1800 0 0 1 &mpic 4 1
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1800 0 0 2 &mpic 1 1
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1800 0 0 3 &mpic 2 1
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1800 0 0 4 &mpic 3 1
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/* IDSEL 0x04 */
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2000 0 0 1 &mpic 3 1
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2000 0 0 2 &mpic 4 1
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2000 0 0 3 &mpic 1 1
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2000 0 0 4 &mpic 2 1
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/* IDSEL 0x05 */
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2800 0 0 1 &mpic 2 1
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2800 0 0 2 &mpic 3 1
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2800 0 0 3 &mpic 4 1
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2800 0 0 4 &mpic 1 1
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/* IDSEL 0x0c */
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6000 0 0 1 &mpic 1 1
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6000 0 0 2 &mpic 2 1
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6000 0 0 3 &mpic 3 1
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6000 0 0 4 &mpic 4 1
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/* IDSEL 0x0d */
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6800 0 0 1 &mpic 4 1
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6800 0 0 2 &mpic 1 1
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6800 0 0 3 &mpic 2 1
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6800 0 0 4 &mpic 3 1
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/* IDSEL 0x0e */
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7000 0 0 1 &mpic 3 1
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7000 0 0 2 &mpic 4 1
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7000 0 0 3 &mpic 1 1
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7000 0 0 4 &mpic 2 1
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/* IDSEL 0x0f */
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7800 0 0 1 &mpic 2 1
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7800 0 0 2 &mpic 3 1
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7800 0 0 3 &mpic 4 1
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7800 0 0 4 &mpic 1 1
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/* IDSEL 0x12 */
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9000 0 0 1 &mpic 1 1
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9000 0 0 2 &mpic 2 1
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9000 0 0 3 &mpic 3 1
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9000 0 0 4 &mpic 4 1
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/* IDSEL 0x13 */
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9800 0 0 1 &mpic 4 1
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9800 0 0 2 &mpic 1 1
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9800 0 0 3 &mpic 2 1
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9800 0 0 4 &mpic 3 1
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/* IDSEL 0x14 */
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a000 0 0 1 &mpic 3 1
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a000 0 0 2 &mpic 4 1
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a000 0 0 3 &mpic 1 1
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a000 0 0 4 &mpic 2 1
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/* IDSEL 0x15 */
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a800 0 0 1 &mpic 2 1
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a800 0 0 2 &mpic 3 1
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a800 0 0 3 &mpic 4 1
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a800 0 0 4 &mpic 1 1>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008000 1000>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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};
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};
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