![Stephen Rothwell](/assets/img/avatar_default.png)
Fixes: e1dba01ca6
("i2c: add generic routine to parse DT for timing information")
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
813 lines
19 KiB
C
813 lines
19 KiB
C
/*
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* drivers/i2c/busses/i2c-ibm_iic.c
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*
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* Support for the IIC peripheral on IBM PPC 4xx
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*
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* Copyright (c) 2003, 2004 Zultys Technologies.
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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*
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* Copyright (c) 2008 PIKA Technologies
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* Sean MacLennan <smaclennan@pikatech.com>
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*
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* Based on original work by
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* Ian DaSilva <idasilva@mvista.com>
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* Armin Kuster <akuster@mvista.com>
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* Matt Porter <mporter@mvista.com>
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*
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* Copyright 2000-2003 MontaVista Software Inc.
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*
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* Original driver version was highly leveraged from i2c-elektor.c
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*
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* Copyright 1995-97 Simon G. Vogl
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* 1998-99 Hans Berglund
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*
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* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
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* and even Frodo Looijaard <frodol@dds.nl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include "i2c-ibm_iic.h"
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#define DRIVER_VERSION "2.2"
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MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
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MODULE_LICENSE("GPL");
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static bool iic_force_poll;
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module_param(iic_force_poll, bool, 0);
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MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
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static bool iic_force_fast;
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module_param(iic_force_fast, bool, 0);
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MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)");
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#define DBG_LEVEL 0
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#ifdef DBG
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#undef DBG
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#endif
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#ifdef DBG2
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#undef DBG2
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#endif
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#if DBG_LEVEL > 0
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# define DBG(f,x...) printk(KERN_DEBUG "ibm-iic" f, ##x)
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#else
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# define DBG(f,x...) ((void)0)
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#endif
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#if DBG_LEVEL > 1
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# define DBG2(f,x...) DBG(f, ##x)
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#else
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# define DBG2(f,x...) ((void)0)
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#endif
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#if DBG_LEVEL > 2
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static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
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{
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
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printk(KERN_DEBUG
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" cntl = 0x%02x, mdcntl = 0x%02x\n"
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" sts = 0x%02x, extsts = 0x%02x\n"
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" clkdiv = 0x%02x, xfrcnt = 0x%02x\n"
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" xtcntlss = 0x%02x, directcntl = 0x%02x\n",
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in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
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in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
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in_8(&iic->xtcntlss), in_8(&iic->directcntl));
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}
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# define DUMP_REGS(h,dev) dump_iic_regs((h),(dev))
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#else
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# define DUMP_REGS(h,dev) ((void)0)
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#endif
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/* Bus timings (in ns) for bit-banging */
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static struct ibm_iic_timings {
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unsigned int hd_sta;
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unsigned int su_sto;
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unsigned int low;
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unsigned int high;
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unsigned int buf;
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} timings [] = {
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/* Standard mode (100 KHz) */
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{
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.hd_sta = 4000,
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.su_sto = 4000,
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.low = 4700,
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.high = 4000,
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.buf = 4700,
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},
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/* Fast mode (400 KHz) */
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{
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.hd_sta = 600,
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.su_sto = 600,
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.low = 1300,
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.high = 600,
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.buf = 1300,
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}};
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/* Enable/disable interrupt generation */
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static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
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{
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out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
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}
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/*
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* Initialize IIC interface.
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*/
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static void iic_dev_init(struct ibm_iic_private* dev)
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{
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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DBG("%d: init\n", dev->idx);
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/* Clear master address */
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out_8(&iic->lmadr, 0);
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out_8(&iic->hmadr, 0);
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/* Clear slave address */
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out_8(&iic->lsadr, 0);
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out_8(&iic->hsadr, 0);
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/* Clear status & extended status */
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out_8(&iic->sts, STS_SCMP | STS_IRQA);
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out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
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| EXTSTS_ICT | EXTSTS_XFRA);
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/* Set clock divider */
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out_8(&iic->clkdiv, dev->clckdiv);
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/* Clear transfer count */
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out_8(&iic->xfrcnt, 0);
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/* Clear extended control and status */
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out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
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| XTCNTLSS_SWS);
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/* Clear control register */
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out_8(&iic->cntl, 0);
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/* Enable interrupts if possible */
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iic_interrupt_mode(dev, dev->irq >= 0);
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/* Set mode control */
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out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
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| (dev->fast_mode ? MDCNTL_FSM : 0));
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DUMP_REGS("iic_init", dev);
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}
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/*
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* Reset IIC interface
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*/
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static void iic_dev_reset(struct ibm_iic_private* dev)
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{
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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int i;
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u8 dc;
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DBG("%d: soft reset\n", dev->idx);
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DUMP_REGS("reset", dev);
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/* Place chip in the reset state */
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out_8(&iic->xtcntlss, XTCNTLSS_SRST);
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/* Check if bus is free */
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dc = in_8(&iic->directcntl);
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if (!DIRCTNL_FREE(dc)){
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DBG("%d: trying to regain bus control\n", dev->idx);
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/* Try to set bus free state */
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out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
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/* Wait until we regain bus control */
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for (i = 0; i < 100; ++i){
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dc = in_8(&iic->directcntl);
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if (DIRCTNL_FREE(dc))
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break;
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/* Toggle SCL line */
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dc ^= DIRCNTL_SCC;
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out_8(&iic->directcntl, dc);
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udelay(10);
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dc ^= DIRCNTL_SCC;
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out_8(&iic->directcntl, dc);
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/* be nice */
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cond_resched();
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}
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}
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/* Remove reset */
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out_8(&iic->xtcntlss, 0);
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/* Reinitialize interface */
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iic_dev_init(dev);
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}
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/*
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* Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
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*/
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/* Wait for SCL and/or SDA to be high */
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static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
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{
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unsigned long x = jiffies + HZ / 28 + 2;
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while ((in_8(&iic->directcntl) & mask) != mask){
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if (unlikely(time_after(jiffies, x)))
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return -1;
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cond_resched();
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}
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return 0;
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}
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static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
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{
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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const struct ibm_iic_timings *t = &timings[dev->fast_mode ? 1 : 0];
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u8 mask, v, sda;
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int i, res;
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/* Only 7-bit addresses are supported */
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if (unlikely(p->flags & I2C_M_TEN)){
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DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
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dev->idx);
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return -EINVAL;
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}
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DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
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/* Reset IIC interface */
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out_8(&iic->xtcntlss, XTCNTLSS_SRST);
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/* Wait for bus to become free */
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out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
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if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
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goto err;
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ndelay(t->buf);
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/* START */
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out_8(&iic->directcntl, DIRCNTL_SCC);
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sda = 0;
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ndelay(t->hd_sta);
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/* Send address */
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v = (u8)((p->addr << 1) | ((p->flags & I2C_M_RD) ? 1 : 0));
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for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
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out_8(&iic->directcntl, sda);
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ndelay(t->low / 2);
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sda = (v & mask) ? DIRCNTL_SDAC : 0;
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out_8(&iic->directcntl, sda);
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ndelay(t->low / 2);
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out_8(&iic->directcntl, DIRCNTL_SCC | sda);
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if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
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goto err;
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ndelay(t->high);
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}
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/* ACK */
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out_8(&iic->directcntl, sda);
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ndelay(t->low / 2);
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out_8(&iic->directcntl, DIRCNTL_SDAC);
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ndelay(t->low / 2);
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out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
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if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
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goto err;
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res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
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ndelay(t->high);
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/* STOP */
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out_8(&iic->directcntl, 0);
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ndelay(t->low);
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out_8(&iic->directcntl, DIRCNTL_SCC);
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if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
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goto err;
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ndelay(t->su_sto);
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out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
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ndelay(t->buf);
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DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
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out:
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/* Remove reset */
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out_8(&iic->xtcntlss, 0);
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/* Reinitialize interface */
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iic_dev_init(dev);
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return res;
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err:
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DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
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res = -EREMOTEIO;
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goto out;
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}
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/*
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* IIC interrupt handler
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*/
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static irqreturn_t iic_handler(int irq, void *dev_id)
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{
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struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
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dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
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/* Acknowledge IRQ and wakeup iic_wait_for_tc */
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out_8(&iic->sts, STS_IRQA | STS_SCMP);
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wake_up_interruptible(&dev->wq);
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return IRQ_HANDLED;
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}
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/*
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* Get master transfer result and clear errors if any.
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* Returns the number of actually transferred bytes or error (<0)
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*/
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static int iic_xfer_result(struct ibm_iic_private* dev)
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{
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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if (unlikely(in_8(&iic->sts) & STS_ERR)){
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DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
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in_8(&iic->extsts));
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/* Clear errors and possible pending IRQs */
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out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
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EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
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/* Flush master data buffer */
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out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
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/* Is bus free?
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* If error happened during combined xfer
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* IIC interface is usually stuck in some strange
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* state, the only way out - soft reset.
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*/
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if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
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DBG("%d: bus is stuck, resetting\n", dev->idx);
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iic_dev_reset(dev);
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}
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return -EREMOTEIO;
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}
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else
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return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
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}
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/*
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* Try to abort active transfer.
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*/
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static void iic_abort_xfer(struct ibm_iic_private* dev)
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{
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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unsigned long x;
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DBG("%d: iic_abort_xfer\n", dev->idx);
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out_8(&iic->cntl, CNTL_HMT);
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/*
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* Wait for the abort command to complete.
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* It's not worth to be optimized, just poll (timeout >= 1 tick)
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*/
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x = jiffies + 2;
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while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
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if (time_after(jiffies, x)){
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DBG("%d: abort timeout, resetting...\n", dev->idx);
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iic_dev_reset(dev);
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return;
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}
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schedule();
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}
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/* Just to clear errors */
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iic_xfer_result(dev);
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}
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/*
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* Wait for master transfer to complete.
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* It puts current process to sleep until we get interrupt or timeout expires.
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* Returns the number of transferred bytes or error (<0)
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*/
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static int iic_wait_for_tc(struct ibm_iic_private* dev){
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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int ret = 0;
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if (dev->irq >= 0){
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/* Interrupt mode */
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ret = wait_event_interruptible_timeout(dev->wq,
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!(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
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if (unlikely(ret < 0))
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DBG("%d: wait interrupted\n", dev->idx);
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else if (unlikely(in_8(&iic->sts) & STS_PT)){
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DBG("%d: wait timeout\n", dev->idx);
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ret = -ETIMEDOUT;
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}
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}
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else {
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/* Polling mode */
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unsigned long x = jiffies + dev->adap.timeout;
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while (in_8(&iic->sts) & STS_PT){
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if (unlikely(time_after(jiffies, x))){
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DBG("%d: poll timeout\n", dev->idx);
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ret = -ETIMEDOUT;
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break;
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}
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if (unlikely(signal_pending(current))){
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DBG("%d: poll interrupted\n", dev->idx);
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ret = -ERESTARTSYS;
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break;
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}
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schedule();
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}
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}
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if (unlikely(ret < 0))
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iic_abort_xfer(dev);
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else
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ret = iic_xfer_result(dev);
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DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
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return ret;
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}
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/*
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* Low level master transfer routine
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*/
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static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
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int combined_xfer)
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{
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volatile struct iic_regs __iomem *iic = dev->vaddr;
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char* buf = pm->buf;
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int i, j, loops, ret = 0;
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int len = pm->len;
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u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
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if (pm->flags & I2C_M_RD)
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cntl |= CNTL_RW;
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loops = (len + 3) / 4;
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for (i = 0; i < loops; ++i, len -= 4){
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int count = len > 4 ? 4 : len;
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u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
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if (!(cntl & CNTL_RW))
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for (j = 0; j < count; ++j)
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out_8((void __iomem *)&iic->mdbuf, *buf++);
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if (i < loops - 1)
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cmd |= CNTL_CHT;
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else if (combined_xfer)
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cmd |= CNTL_RPST;
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DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
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|
|
|
/* Start transfer */
|
|
out_8(&iic->cntl, cmd);
|
|
|
|
/* Wait for completion */
|
|
ret = iic_wait_for_tc(dev);
|
|
|
|
if (unlikely(ret < 0))
|
|
break;
|
|
else if (unlikely(ret != count)){
|
|
DBG("%d: xfer_bytes, requested %d, transferred %d\n",
|
|
dev->idx, count, ret);
|
|
|
|
/* If it's not a last part of xfer, abort it */
|
|
if (combined_xfer || (i < loops - 1))
|
|
iic_abort_xfer(dev);
|
|
|
|
ret = -EREMOTEIO;
|
|
break;
|
|
}
|
|
|
|
if (cntl & CNTL_RW)
|
|
for (j = 0; j < count; ++j)
|
|
*buf++ = in_8((void __iomem *)&iic->mdbuf);
|
|
}
|
|
|
|
return ret > 0 ? 0 : ret;
|
|
}
|
|
|
|
/*
|
|
* Set target slave address for master transfer
|
|
*/
|
|
static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
|
|
{
|
|
volatile struct iic_regs __iomem *iic = dev->vaddr;
|
|
u16 addr = msg->addr;
|
|
|
|
DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
|
|
addr, msg->flags & I2C_M_TEN ? 10 : 7);
|
|
|
|
if (msg->flags & I2C_M_TEN){
|
|
out_8(&iic->cntl, CNTL_AMD);
|
|
out_8(&iic->lmadr, addr);
|
|
out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
|
|
}
|
|
else {
|
|
out_8(&iic->cntl, 0);
|
|
out_8(&iic->lmadr, addr << 1);
|
|
}
|
|
}
|
|
|
|
static inline int iic_invalid_address(const struct i2c_msg* p)
|
|
{
|
|
return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
|
|
}
|
|
|
|
static inline int iic_address_neq(const struct i2c_msg* p1,
|
|
const struct i2c_msg* p2)
|
|
{
|
|
return (p1->addr != p2->addr)
|
|
|| ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
|
|
}
|
|
|
|
/*
|
|
* Generic master transfer entrypoint.
|
|
* Returns the number of processed messages or error (<0)
|
|
*/
|
|
static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
{
|
|
struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
|
|
volatile struct iic_regs __iomem *iic = dev->vaddr;
|
|
int i, ret = 0;
|
|
|
|
DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
|
|
|
|
if (!num)
|
|
return 0;
|
|
|
|
/* Check the sanity of the passed messages.
|
|
* Uhh, generic i2c layer is more suitable place for such code...
|
|
*/
|
|
if (unlikely(iic_invalid_address(&msgs[0]))){
|
|
DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
|
|
msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
|
|
return -EINVAL;
|
|
}
|
|
for (i = 0; i < num; ++i){
|
|
if (unlikely(msgs[i].len <= 0)){
|
|
if (num == 1 && !msgs[0].len){
|
|
/* Special case for I2C_SMBUS_QUICK emulation.
|
|
* IBM IIC doesn't support 0-length transactions
|
|
* so we have to emulate them using bit-banging.
|
|
*/
|
|
return iic_smbus_quick(dev, &msgs[0]);
|
|
}
|
|
DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
|
|
msgs[i].len, i);
|
|
return -EINVAL;
|
|
}
|
|
if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
|
|
DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* Check bus state */
|
|
if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
|
|
DBG("%d: iic_xfer, bus is not free\n", dev->idx);
|
|
|
|
/* Usually it means something serious has happened.
|
|
* We *cannot* have unfinished previous transfer
|
|
* so it doesn't make any sense to try to stop it.
|
|
* Probably we were not able to recover from the
|
|
* previous error.
|
|
* The only *reasonable* thing I can think of here
|
|
* is soft reset. --ebs
|
|
*/
|
|
iic_dev_reset(dev);
|
|
|
|
if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
|
|
DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
else {
|
|
/* Flush master data buffer (just in case) */
|
|
out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
|
|
}
|
|
|
|
/* Load slave address */
|
|
iic_address(dev, &msgs[0]);
|
|
|
|
/* Do real transfer */
|
|
for (i = 0; i < num && !ret; ++i)
|
|
ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
|
|
|
|
return ret < 0 ? ret : num;
|
|
}
|
|
|
|
static u32 iic_func(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
|
|
}
|
|
|
|
static const struct i2c_algorithm iic_algo = {
|
|
.master_xfer = iic_xfer,
|
|
.functionality = iic_func
|
|
};
|
|
|
|
/*
|
|
* Calculates IICx_CLCKDIV value for a specific OPB clock frequency
|
|
*/
|
|
static inline u8 iic_clckdiv(unsigned int opb)
|
|
{
|
|
/* Compatibility kludge, should go away after all cards
|
|
* are fixed to fill correct value for opbfreq.
|
|
* Previous driver version used hardcoded divider value 4,
|
|
* it corresponds to OPB frequency from the range (40, 50] MHz
|
|
*/
|
|
if (!opb){
|
|
printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
|
|
" fix your board specific setup\n");
|
|
opb = 50000000;
|
|
}
|
|
|
|
/* Convert to MHz */
|
|
opb /= 1000000;
|
|
|
|
if (opb < 20 || opb > 150){
|
|
printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
|
|
opb);
|
|
opb = opb < 20 ? 20 : 150;
|
|
}
|
|
return (u8)((opb + 9) / 10 - 1);
|
|
}
|
|
|
|
static int iic_request_irq(struct platform_device *ofdev,
|
|
struct ibm_iic_private *dev)
|
|
{
|
|
struct device_node *np = ofdev->dev.of_node;
|
|
int irq;
|
|
|
|
if (iic_force_poll)
|
|
return 0;
|
|
|
|
irq = irq_of_parse_and_map(np, 0);
|
|
if (!irq) {
|
|
dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Disable interrupts until we finish initialization, assumes
|
|
* level-sensitive IRQ setup...
|
|
*/
|
|
iic_interrupt_mode(dev, 0);
|
|
if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
|
|
dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
|
|
/* Fallback to the polling mode */
|
|
return 0;
|
|
}
|
|
|
|
return irq;
|
|
}
|
|
|
|
/*
|
|
* Register single IIC interface
|
|
*/
|
|
static int iic_probe(struct platform_device *ofdev)
|
|
{
|
|
struct device_node *np = ofdev->dev.of_node;
|
|
struct ibm_iic_private *dev;
|
|
struct i2c_adapter *adap;
|
|
const u32 *freq;
|
|
int ret;
|
|
|
|
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
|
|
if (!dev) {
|
|
dev_err(&ofdev->dev, "failed to allocate device data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
platform_set_drvdata(ofdev, dev);
|
|
|
|
dev->vaddr = of_iomap(np, 0);
|
|
if (dev->vaddr == NULL) {
|
|
dev_err(&ofdev->dev, "failed to iomap device\n");
|
|
ret = -ENXIO;
|
|
goto error_cleanup;
|
|
}
|
|
|
|
init_waitqueue_head(&dev->wq);
|
|
|
|
dev->irq = iic_request_irq(ofdev, dev);
|
|
if (!dev->irq)
|
|
dev_warn(&ofdev->dev, "using polling mode\n");
|
|
|
|
/* Board specific settings */
|
|
if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
|
|
dev->fast_mode = 1;
|
|
|
|
freq = of_get_property(np, "clock-frequency", NULL);
|
|
if (freq == NULL) {
|
|
freq = of_get_property(np->parent, "clock-frequency", NULL);
|
|
if (freq == NULL) {
|
|
dev_err(&ofdev->dev, "Unable to get bus frequency\n");
|
|
ret = -EINVAL;
|
|
goto error_cleanup;
|
|
}
|
|
}
|
|
|
|
dev->clckdiv = iic_clckdiv(*freq);
|
|
dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
|
|
|
|
/* Initialize IIC interface */
|
|
iic_dev_init(dev);
|
|
|
|
/* Register it with i2c layer */
|
|
adap = &dev->adap;
|
|
adap->dev.parent = &ofdev->dev;
|
|
adap->dev.of_node = of_node_get(np);
|
|
strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
|
|
i2c_set_adapdata(adap, dev);
|
|
adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
|
adap->algo = &iic_algo;
|
|
adap->timeout = HZ;
|
|
|
|
ret = i2c_add_adapter(adap);
|
|
if (ret < 0) {
|
|
dev_err(&ofdev->dev, "failed to register i2c adapter\n");
|
|
goto error_cleanup;
|
|
}
|
|
|
|
dev_info(&ofdev->dev, "using %s mode\n",
|
|
dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
|
|
|
|
return 0;
|
|
|
|
error_cleanup:
|
|
if (dev->irq) {
|
|
iic_interrupt_mode(dev, 0);
|
|
free_irq(dev->irq, dev);
|
|
}
|
|
|
|
if (dev->vaddr)
|
|
iounmap(dev->vaddr);
|
|
|
|
kfree(dev);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Cleanup initialized IIC interface
|
|
*/
|
|
static int iic_remove(struct platform_device *ofdev)
|
|
{
|
|
struct ibm_iic_private *dev = platform_get_drvdata(ofdev);
|
|
|
|
i2c_del_adapter(&dev->adap);
|
|
|
|
if (dev->irq) {
|
|
iic_interrupt_mode(dev, 0);
|
|
free_irq(dev->irq, dev);
|
|
}
|
|
|
|
iounmap(dev->vaddr);
|
|
kfree(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id ibm_iic_match[] = {
|
|
{ .compatible = "ibm,iic", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ibm_iic_match);
|
|
|
|
static struct platform_driver ibm_iic_driver = {
|
|
.driver = {
|
|
.name = "ibm-iic",
|
|
.of_match_table = ibm_iic_match,
|
|
},
|
|
.probe = iic_probe,
|
|
.remove = iic_remove,
|
|
};
|
|
|
|
module_platform_driver(ibm_iic_driver);
|