![Wolfram Sang](/assets/img/avatar_default.png)
Enable the I2C core for this SoC. It is compitable to Gen2 SoCs, so reuse the settings. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
1047 lines
29 KiB
C
1047 lines
29 KiB
C
/*
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* SuperH Mobile I2C Controller
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*
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* Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
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*
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* Copyright (C) 2008 Magnus Damm
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*
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* Portions of the code based on out-of-tree driver i2c-sh7343.c
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* Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/i2c/i2c-sh_mobile.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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/* Transmit operation: */
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/* */
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/* 0 byte transmit */
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/* BUS: S A8 ACK P(*) */
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/* IRQ: DTE WAIT */
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/* ICIC: */
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/* ICCR: 0x94 0x90 */
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/* ICDR: A8 */
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/* */
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/* 1 byte transmit */
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/* BUS: S A8 ACK D8(1) ACK P(*) */
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/* IRQ: DTE WAIT WAIT */
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/* ICIC: -DTE */
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/* ICCR: 0x94 0x90 */
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/* ICDR: A8 D8(1) */
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/* */
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/* 2 byte transmit */
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/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
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/* IRQ: DTE WAIT WAIT WAIT */
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/* ICIC: -DTE */
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/* ICCR: 0x94 0x90 */
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/* ICDR: A8 D8(1) D8(2) */
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/* */
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/* 3 bytes or more, +---------+ gets repeated */
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/* */
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/* */
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/* Receive operation: */
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/* */
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/* 0 byte receive - not supported since slave may hold SDA low */
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/* */
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/* 1 byte receive [TX] | [RX] */
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/* BUS: S A8 ACK | D8(1) ACK P(*) */
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/* IRQ: DTE WAIT | WAIT DTE */
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/* ICIC: -DTE | +DTE */
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/* ICCR: 0x94 0x81 | 0xc0 */
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/* ICDR: A8 | D8(1) */
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/* */
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/* 2 byte receive [TX]| [RX] */
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/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
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/* IRQ: DTE WAIT | WAIT WAIT DTE */
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/* ICIC: -DTE | +DTE */
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/* ICCR: 0x94 0x81 | 0xc0 */
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/* ICDR: A8 | D8(1) D8(2) */
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/* */
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/* 3 byte receive [TX] | [RX] (*) */
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/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
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/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
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/* ICIC: -DTE | +DTE */
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/* ICCR: 0x94 0x81 | 0xc0 */
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/* ICDR: A8 | D8(1) D8(2) D8(3) */
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/* */
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/* 4 bytes or more, this part is repeated +---------+ */
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/* */
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/* */
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/* Interrupt order and BUSY flag */
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/* ___ _ */
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/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
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/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
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/* */
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/* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
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/* ___ */
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/* WAIT IRQ ________________________________/ \___________ */
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/* TACK IRQ ____________________________________/ \_______ */
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/* DTE IRQ __________________________________________/ \_ */
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/* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
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/* _______________________________________________ */
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/* BUSY __/ \_ */
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/* */
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/* (*) The STOP condition is only sent by the master at the end of the last */
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/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
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/* only cleared after the STOP condition, so, between messages we have to */
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/* poll for the DTE bit. */
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/* */
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enum sh_mobile_i2c_op {
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OP_START = 0,
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OP_TX_FIRST,
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OP_TX,
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OP_TX_STOP,
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OP_TX_STOP_DATA,
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OP_TX_TO_RX,
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OP_RX,
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OP_RX_STOP,
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OP_RX_STOP_DATA,
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};
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struct sh_mobile_i2c_data {
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struct device *dev;
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void __iomem *reg;
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struct i2c_adapter adap;
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unsigned long bus_speed;
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unsigned int clks_per_count;
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struct clk *clk;
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u_int8_t icic;
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u_int8_t flags;
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u_int16_t iccl;
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u_int16_t icch;
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spinlock_t lock;
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wait_queue_head_t wait;
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struct i2c_msg *msg;
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int pos;
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int sr;
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bool send_stop;
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bool stop_after_dma;
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struct resource *res;
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struct dma_chan *dma_tx;
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struct dma_chan *dma_rx;
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struct scatterlist sg;
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enum dma_data_direction dma_direction;
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};
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struct sh_mobile_dt_config {
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int clks_per_count;
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void (*setup)(struct sh_mobile_i2c_data *pd);
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};
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#define IIC_FLAG_HAS_ICIC67 (1 << 0)
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#define STANDARD_MODE 100000
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#define FAST_MODE 400000
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/* Register offsets */
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#define ICDR 0x00
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#define ICCR 0x04
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#define ICSR 0x08
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#define ICIC 0x0c
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#define ICCL 0x10
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#define ICCH 0x14
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#define ICSTART 0x70
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/* Register bits */
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#define ICCR_ICE 0x80
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#define ICCR_RACK 0x40
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#define ICCR_TRS 0x10
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#define ICCR_BBSY 0x04
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#define ICCR_SCP 0x01
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#define ICSR_SCLM 0x80
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#define ICSR_SDAM 0x40
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#define SW_DONE 0x20
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#define ICSR_BUSY 0x10
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#define ICSR_AL 0x08
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#define ICSR_TACK 0x04
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#define ICSR_WAIT 0x02
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#define ICSR_DTE 0x01
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#define ICIC_ICCLB8 0x80
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#define ICIC_ICCHB8 0x40
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#define ICIC_TDMAE 0x20
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#define ICIC_RDMAE 0x10
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#define ICIC_ALE 0x08
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#define ICIC_TACKE 0x04
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#define ICIC_WAITE 0x02
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#define ICIC_DTEE 0x01
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#define ICSTART_ICSTART 0x10
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static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
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{
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if (offs == ICIC)
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data |= pd->icic;
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iowrite8(data, pd->reg + offs);
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}
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static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
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{
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return ioread8(pd->reg + offs);
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}
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static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
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unsigned char set, unsigned char clr)
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{
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iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
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}
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static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
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{
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/*
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* Conditional expression:
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* ICCL >= COUNT_CLK * (tLOW + tf)
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*
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* SH-Mobile IIC hardware starts counting the LOW period of
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* the SCL signal (tLOW) as soon as it pulls the SCL line.
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* In order to meet the tLOW timing spec, we need to take into
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* account the fall time of SCL signal (tf). Default tf value
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* should be 0.3 us, for safety.
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*/
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return (((count_khz * (tLOW + tf)) + 5000) / 10000);
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}
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static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
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{
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/*
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* Conditional expression:
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* ICCH >= COUNT_CLK * (tHIGH + tf)
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*
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* SH-Mobile IIC hardware is aware of SCL transition period 'tr',
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* and can ignore it. SH-Mobile IIC controller starts counting
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* the HIGH period of the SCL signal (tHIGH) after the SCL input
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* voltage increases at VIH.
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*
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* Afterward it turned out calculating ICCH using only tHIGH spec
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* will result in violation of the tHD;STA timing spec. We need
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* to take into account the fall time of SDA signal (tf) at START
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* condition, in order to meet both tHIGH and tHD;STA specs.
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*/
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return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
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}
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static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
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{
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unsigned long i2c_clk_khz;
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u32 tHIGH, tLOW, tf;
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uint16_t max_val;
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/* Get clock rate after clock is enabled */
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clk_prepare_enable(pd->clk);
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i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
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clk_disable_unprepare(pd->clk);
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i2c_clk_khz /= pd->clks_per_count;
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if (pd->bus_speed == STANDARD_MODE) {
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tLOW = 47; /* tLOW = 4.7 us */
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tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
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tf = 3; /* tf = 0.3 us */
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} else if (pd->bus_speed == FAST_MODE) {
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tLOW = 13; /* tLOW = 1.3 us */
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tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
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tf = 3; /* tf = 0.3 us */
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} else {
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dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
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pd->bus_speed);
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return -EINVAL;
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}
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pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
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pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
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max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
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if (pd->iccl > max_val || pd->icch > max_val) {
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dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
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pd->iccl, pd->icch);
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return -EINVAL;
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}
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/* one more bit of ICCL in ICIC */
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if (pd->iccl & 0x100)
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pd->icic |= ICIC_ICCLB8;
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else
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pd->icic &= ~ICIC_ICCLB8;
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/* one more bit of ICCH in ICIC */
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if (pd->icch & 0x100)
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pd->icic |= ICIC_ICCHB8;
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else
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pd->icic &= ~ICIC_ICCHB8;
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dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
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return 0;
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}
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static void activate_ch(struct sh_mobile_i2c_data *pd)
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{
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/* Wake up device and enable clock */
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pm_runtime_get_sync(pd->dev);
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clk_prepare_enable(pd->clk);
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/* Enable channel and configure rx ack */
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iic_set_clr(pd, ICCR, ICCR_ICE, 0);
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/* Mask all interrupts */
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iic_wr(pd, ICIC, 0);
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/* Set the clock */
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iic_wr(pd, ICCL, pd->iccl & 0xff);
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iic_wr(pd, ICCH, pd->icch & 0xff);
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}
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static void deactivate_ch(struct sh_mobile_i2c_data *pd)
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{
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/* Clear/disable interrupts */
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iic_wr(pd, ICSR, 0);
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iic_wr(pd, ICIC, 0);
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/* Disable channel */
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iic_set_clr(pd, ICCR, 0, ICCR_ICE);
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/* Disable clock and mark device as idle */
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clk_disable_unprepare(pd->clk);
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pm_runtime_put_sync(pd->dev);
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}
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static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
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enum sh_mobile_i2c_op op, unsigned char data)
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{
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unsigned char ret = 0;
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unsigned long flags;
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dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
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spin_lock_irqsave(&pd->lock, flags);
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switch (op) {
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case OP_START: /* issue start and trigger DTE interrupt */
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iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
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break;
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case OP_TX_FIRST: /* disable DTE interrupt and write data */
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iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
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iic_wr(pd, ICDR, data);
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break;
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case OP_TX: /* write data */
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iic_wr(pd, ICDR, data);
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break;
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case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
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iic_wr(pd, ICDR, data);
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/* fallthrough */
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case OP_TX_STOP: /* issue a stop */
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iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
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: ICCR_ICE | ICCR_TRS | ICCR_BBSY);
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break;
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case OP_TX_TO_RX: /* select read mode */
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iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
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break;
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case OP_RX: /* just read data */
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ret = iic_rd(pd, ICDR);
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break;
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case OP_RX_STOP: /* enable DTE interrupt, issue stop */
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iic_wr(pd, ICIC,
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ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
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iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
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break;
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case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
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iic_wr(pd, ICIC,
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ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
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ret = iic_rd(pd, ICDR);
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iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
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break;
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}
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spin_unlock_irqrestore(&pd->lock, flags);
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dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
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return ret;
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}
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static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
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{
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return pd->pos == -1;
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}
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static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
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{
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return pd->pos == pd->msg->len - 1;
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}
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static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
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unsigned char *buf)
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{
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switch (pd->pos) {
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case -1:
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*buf = (pd->msg->addr & 0x7f) << 1;
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*buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
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break;
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default:
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*buf = pd->msg->buf[pd->pos];
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}
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}
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static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
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{
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unsigned char data;
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if (pd->pos == pd->msg->len) {
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/* Send stop if we haven't yet (DMA case) */
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if (pd->send_stop && pd->stop_after_dma)
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i2c_op(pd, OP_TX_STOP, 0);
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return 1;
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}
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sh_mobile_i2c_get_data(pd, &data);
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if (sh_mobile_i2c_is_last_byte(pd))
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i2c_op(pd, OP_TX_STOP_DATA, data);
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else if (sh_mobile_i2c_is_first_byte(pd))
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i2c_op(pd, OP_TX_FIRST, data);
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else
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i2c_op(pd, OP_TX, data);
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pd->pos++;
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return 0;
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}
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static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
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{
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unsigned char data;
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int real_pos;
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do {
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if (pd->pos <= -1) {
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sh_mobile_i2c_get_data(pd, &data);
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if (sh_mobile_i2c_is_first_byte(pd))
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i2c_op(pd, OP_TX_FIRST, data);
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else
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i2c_op(pd, OP_TX, data);
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break;
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}
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if (pd->pos == 0) {
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i2c_op(pd, OP_TX_TO_RX, 0);
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break;
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}
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real_pos = pd->pos - 2;
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if (pd->pos == pd->msg->len) {
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if (pd->stop_after_dma) {
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/* Simulate PIO end condition after DMA transfer */
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i2c_op(pd, OP_RX_STOP, 0);
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pd->pos++;
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break;
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}
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if (real_pos < 0) {
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i2c_op(pd, OP_RX_STOP, 0);
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break;
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}
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data = i2c_op(pd, OP_RX_STOP_DATA, 0);
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} else
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data = i2c_op(pd, OP_RX, 0);
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if (real_pos >= 0)
|
|
pd->msg->buf[real_pos] = data;
|
|
} while (0);
|
|
|
|
pd->pos++;
|
|
return pd->pos == (pd->msg->len + 2);
|
|
}
|
|
|
|
static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
|
|
{
|
|
struct sh_mobile_i2c_data *pd = dev_id;
|
|
unsigned char sr;
|
|
int wakeup = 0;
|
|
|
|
sr = iic_rd(pd, ICSR);
|
|
pd->sr |= sr; /* remember state */
|
|
|
|
dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
|
|
(pd->msg->flags & I2C_M_RD) ? "read" : "write",
|
|
pd->pos, pd->msg->len);
|
|
|
|
/* Kick off TxDMA after preface was done */
|
|
if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
|
|
iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
|
|
else if (sr & (ICSR_AL | ICSR_TACK))
|
|
/* don't interrupt transaction - continue to issue stop */
|
|
iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
|
|
else if (pd->msg->flags & I2C_M_RD)
|
|
wakeup = sh_mobile_i2c_isr_rx(pd);
|
|
else
|
|
wakeup = sh_mobile_i2c_isr_tx(pd);
|
|
|
|
/* Kick off RxDMA after preface was done */
|
|
if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
|
|
iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
|
|
|
|
if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
|
|
iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
|
|
|
|
if (wakeup) {
|
|
pd->sr |= SW_DONE;
|
|
wake_up(&pd->wait);
|
|
}
|
|
|
|
/* defeat write posting to avoid spurious WAIT interrupts */
|
|
iic_rd(pd, ICSR);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
|
|
{
|
|
struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
|
|
? pd->dma_rx : pd->dma_tx;
|
|
|
|
dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
|
|
pd->msg->len, pd->dma_direction);
|
|
|
|
pd->dma_direction = DMA_NONE;
|
|
}
|
|
|
|
static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
|
|
{
|
|
if (pd->dma_direction == DMA_NONE)
|
|
return;
|
|
else if (pd->dma_direction == DMA_FROM_DEVICE)
|
|
dmaengine_terminate_all(pd->dma_rx);
|
|
else if (pd->dma_direction == DMA_TO_DEVICE)
|
|
dmaengine_terminate_all(pd->dma_tx);
|
|
|
|
sh_mobile_i2c_dma_unmap(pd);
|
|
}
|
|
|
|
static void sh_mobile_i2c_dma_callback(void *data)
|
|
{
|
|
struct sh_mobile_i2c_data *pd = data;
|
|
|
|
sh_mobile_i2c_dma_unmap(pd);
|
|
pd->pos = pd->msg->len;
|
|
pd->stop_after_dma = true;
|
|
|
|
iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
|
|
}
|
|
|
|
static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
|
|
enum dma_transfer_direction dir, dma_addr_t port_addr)
|
|
{
|
|
struct dma_chan *chan;
|
|
struct dma_slave_config cfg;
|
|
char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
|
|
int ret;
|
|
|
|
chan = dma_request_slave_channel_reason(dev, chan_name);
|
|
if (IS_ERR(chan)) {
|
|
ret = PTR_ERR(chan);
|
|
dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
|
|
return chan;
|
|
}
|
|
|
|
memset(&cfg, 0, sizeof(cfg));
|
|
cfg.direction = dir;
|
|
if (dir == DMA_MEM_TO_DEV) {
|
|
cfg.dst_addr = port_addr;
|
|
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
} else {
|
|
cfg.src_addr = port_addr;
|
|
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
}
|
|
|
|
ret = dmaengine_slave_config(chan, &cfg);
|
|
if (ret) {
|
|
dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
|
|
dma_release_channel(chan);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
dev_dbg(dev, "got DMA channel for %s\n", chan_name);
|
|
return chan;
|
|
}
|
|
|
|
static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
|
|
{
|
|
bool read = pd->msg->flags & I2C_M_RD;
|
|
enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
|
|
struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
|
|
struct dma_async_tx_descriptor *txdesc;
|
|
dma_addr_t dma_addr;
|
|
dma_cookie_t cookie;
|
|
|
|
if (PTR_ERR(chan) == -EPROBE_DEFER) {
|
|
if (read)
|
|
chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
|
|
pd->res->start + ICDR);
|
|
else
|
|
chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
|
|
pd->res->start + ICDR);
|
|
}
|
|
|
|
if (IS_ERR(chan))
|
|
return;
|
|
|
|
dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
|
|
if (dma_mapping_error(pd->dev, dma_addr)) {
|
|
dev_dbg(pd->dev, "dma map failed, using PIO\n");
|
|
return;
|
|
}
|
|
|
|
sg_dma_len(&pd->sg) = pd->msg->len;
|
|
sg_dma_address(&pd->sg) = dma_addr;
|
|
|
|
pd->dma_direction = dir;
|
|
|
|
txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
|
|
read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
if (!txdesc) {
|
|
dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
|
|
sh_mobile_i2c_cleanup_dma(pd);
|
|
return;
|
|
}
|
|
|
|
txdesc->callback = sh_mobile_i2c_dma_callback;
|
|
txdesc->callback_param = pd;
|
|
|
|
cookie = dmaengine_submit(txdesc);
|
|
if (dma_submit_error(cookie)) {
|
|
dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
|
|
sh_mobile_i2c_cleanup_dma(pd);
|
|
return;
|
|
}
|
|
|
|
dma_async_issue_pending(chan);
|
|
}
|
|
|
|
static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
|
|
bool do_init)
|
|
{
|
|
if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
|
|
dev_err(pd->dev, "Unsupported zero length i2c read\n");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
if (do_init) {
|
|
/* Initialize channel registers */
|
|
iic_set_clr(pd, ICCR, 0, ICCR_ICE);
|
|
|
|
/* Enable channel and configure rx ack */
|
|
iic_set_clr(pd, ICCR, ICCR_ICE, 0);
|
|
|
|
/* Set the clock */
|
|
iic_wr(pd, ICCL, pd->iccl & 0xff);
|
|
iic_wr(pd, ICCH, pd->icch & 0xff);
|
|
}
|
|
|
|
pd->msg = usr_msg;
|
|
pd->pos = -1;
|
|
pd->sr = 0;
|
|
|
|
if (pd->msg->len > 8)
|
|
sh_mobile_i2c_xfer_dma(pd);
|
|
|
|
/* Enable all interrupts to begin with */
|
|
iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
|
|
return 0;
|
|
}
|
|
|
|
static int poll_dte(struct sh_mobile_i2c_data *pd)
|
|
{
|
|
int i;
|
|
|
|
for (i = 1000; i; i--) {
|
|
u_int8_t val = iic_rd(pd, ICSR);
|
|
|
|
if (val & ICSR_DTE)
|
|
break;
|
|
|
|
if (val & ICSR_TACK)
|
|
return -ENXIO;
|
|
|
|
udelay(10);
|
|
}
|
|
|
|
return i ? 0 : -ETIMEDOUT;
|
|
}
|
|
|
|
static int poll_busy(struct sh_mobile_i2c_data *pd)
|
|
{
|
|
int i;
|
|
|
|
for (i = 1000; i; i--) {
|
|
u_int8_t val = iic_rd(pd, ICSR);
|
|
|
|
dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
|
|
|
|
/* the interrupt handler may wake us up before the
|
|
* transfer is finished, so poll the hardware
|
|
* until we're done.
|
|
*/
|
|
if (!(val & ICSR_BUSY)) {
|
|
/* handle missing acknowledge and arbitration lost */
|
|
val |= pd->sr;
|
|
if (val & ICSR_TACK)
|
|
return -ENXIO;
|
|
if (val & ICSR_AL)
|
|
return -EAGAIN;
|
|
break;
|
|
}
|
|
|
|
udelay(10);
|
|
}
|
|
|
|
return i ? 0 : -ETIMEDOUT;
|
|
}
|
|
|
|
static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
|
|
struct i2c_msg *msgs,
|
|
int num)
|
|
{
|
|
struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
|
|
struct i2c_msg *msg;
|
|
int err = 0;
|
|
int i;
|
|
long timeout;
|
|
|
|
activate_ch(pd);
|
|
|
|
/* Process all messages */
|
|
for (i = 0; i < num; i++) {
|
|
bool do_start = pd->send_stop || !i;
|
|
msg = &msgs[i];
|
|
pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
|
|
pd->stop_after_dma = false;
|
|
|
|
err = start_ch(pd, msg, do_start);
|
|
if (err)
|
|
break;
|
|
|
|
if (do_start)
|
|
i2c_op(pd, OP_START, 0);
|
|
|
|
/* The interrupt handler takes care of the rest... */
|
|
timeout = wait_event_timeout(pd->wait,
|
|
pd->sr & (ICSR_TACK | SW_DONE),
|
|
adapter->timeout);
|
|
if (!timeout) {
|
|
dev_err(pd->dev, "Transfer request timed out\n");
|
|
if (pd->dma_direction != DMA_NONE)
|
|
sh_mobile_i2c_cleanup_dma(pd);
|
|
|
|
err = -ETIMEDOUT;
|
|
break;
|
|
}
|
|
|
|
if (pd->send_stop)
|
|
err = poll_busy(pd);
|
|
else
|
|
err = poll_dte(pd);
|
|
if (err < 0)
|
|
break;
|
|
}
|
|
|
|
deactivate_ch(pd);
|
|
|
|
if (!err)
|
|
err = num;
|
|
return err;
|
|
}
|
|
|
|
static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
|
|
}
|
|
|
|
static struct i2c_algorithm sh_mobile_i2c_algorithm = {
|
|
.functionality = sh_mobile_i2c_func,
|
|
.master_xfer = sh_mobile_i2c_xfer,
|
|
};
|
|
|
|
/*
|
|
* r8a7740 chip has lasting errata on I2C I/O pad reset.
|
|
* this is work-around for it.
|
|
*/
|
|
static void sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
|
|
{
|
|
iic_set_clr(pd, ICCR, ICCR_ICE, 0);
|
|
iic_rd(pd, ICCR); /* dummy read */
|
|
|
|
iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
|
|
iic_rd(pd, ICSTART); /* dummy read */
|
|
|
|
udelay(10);
|
|
|
|
iic_wr(pd, ICCR, ICCR_SCP);
|
|
iic_wr(pd, ICSTART, 0);
|
|
|
|
udelay(10);
|
|
|
|
iic_wr(pd, ICCR, ICCR_TRS);
|
|
udelay(10);
|
|
iic_wr(pd, ICCR, 0);
|
|
udelay(10);
|
|
iic_wr(pd, ICCR, ICCR_TRS);
|
|
udelay(10);
|
|
}
|
|
|
|
static const struct sh_mobile_dt_config default_dt_config = {
|
|
.clks_per_count = 1,
|
|
};
|
|
|
|
static const struct sh_mobile_dt_config fast_clock_dt_config = {
|
|
.clks_per_count = 2,
|
|
};
|
|
|
|
static const struct sh_mobile_dt_config r8a7740_dt_config = {
|
|
.clks_per_count = 1,
|
|
.setup = sh_mobile_i2c_r8a7740_workaround,
|
|
};
|
|
|
|
static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
|
|
{ .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
|
|
{ .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
|
|
{ .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
|
|
{ .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
|
|
{ .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
|
|
{ .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
|
|
{ .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
|
|
{ .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
|
|
{ .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
|
|
{ .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
|
|
|
|
static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
|
|
{
|
|
if (!IS_ERR(pd->dma_tx)) {
|
|
dma_release_channel(pd->dma_tx);
|
|
pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
|
|
}
|
|
|
|
if (!IS_ERR(pd->dma_rx)) {
|
|
dma_release_channel(pd->dma_rx);
|
|
pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
|
|
}
|
|
}
|
|
|
|
static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
|
|
{
|
|
struct resource *res;
|
|
resource_size_t n;
|
|
int k = 0, ret;
|
|
|
|
while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
|
|
for (n = res->start; n <= res->end; n++) {
|
|
ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
|
|
0, dev_name(&dev->dev), pd);
|
|
if (ret) {
|
|
dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
|
|
return ret;
|
|
}
|
|
}
|
|
k++;
|
|
}
|
|
|
|
return k > 0 ? 0 : -ENOENT;
|
|
}
|
|
|
|
static int sh_mobile_i2c_probe(struct platform_device *dev)
|
|
{
|
|
struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
|
|
struct sh_mobile_i2c_data *pd;
|
|
struct i2c_adapter *adap;
|
|
struct resource *res;
|
|
int ret;
|
|
u32 bus_speed;
|
|
|
|
pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
|
|
if (!pd)
|
|
return -ENOMEM;
|
|
|
|
pd->clk = devm_clk_get(&dev->dev, NULL);
|
|
if (IS_ERR(pd->clk)) {
|
|
dev_err(&dev->dev, "cannot get clock\n");
|
|
return PTR_ERR(pd->clk);
|
|
}
|
|
|
|
ret = sh_mobile_i2c_hook_irqs(dev, pd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pd->dev = &dev->dev;
|
|
platform_set_drvdata(dev, pd);
|
|
|
|
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
|
|
|
pd->res = res;
|
|
pd->reg = devm_ioremap_resource(&dev->dev, res);
|
|
if (IS_ERR(pd->reg))
|
|
return PTR_ERR(pd->reg);
|
|
|
|
/* Use platform data bus speed or STANDARD_MODE */
|
|
ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
|
|
pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
|
|
|
|
pd->clks_per_count = 1;
|
|
|
|
if (dev->dev.of_node) {
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
|
|
if (match) {
|
|
const struct sh_mobile_dt_config *config;
|
|
|
|
config = match->data;
|
|
pd->clks_per_count = config->clks_per_count;
|
|
|
|
if (config->setup)
|
|
config->setup(pd);
|
|
}
|
|
} else {
|
|
if (pdata && pdata->bus_speed)
|
|
pd->bus_speed = pdata->bus_speed;
|
|
if (pdata && pdata->clks_per_count)
|
|
pd->clks_per_count = pdata->clks_per_count;
|
|
}
|
|
|
|
/* The IIC blocks on SH-Mobile ARM processors
|
|
* come with two new bits in ICIC.
|
|
*/
|
|
if (resource_size(res) > 0x17)
|
|
pd->flags |= IIC_FLAG_HAS_ICIC67;
|
|
|
|
ret = sh_mobile_i2c_init(pd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Init DMA */
|
|
sg_init_table(&pd->sg, 1);
|
|
pd->dma_direction = DMA_NONE;
|
|
pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
|
|
|
|
/* Enable Runtime PM for this device.
|
|
*
|
|
* Also tell the Runtime PM core to ignore children
|
|
* for this device since it is valid for us to suspend
|
|
* this I2C master driver even though the slave devices
|
|
* on the I2C bus may not be suspended.
|
|
*
|
|
* The state of the I2C hardware bus is unaffected by
|
|
* the Runtime PM state.
|
|
*/
|
|
pm_suspend_ignore_children(&dev->dev, true);
|
|
pm_runtime_enable(&dev->dev);
|
|
|
|
/* setup the private data */
|
|
adap = &pd->adap;
|
|
i2c_set_adapdata(adap, pd);
|
|
|
|
adap->owner = THIS_MODULE;
|
|
adap->algo = &sh_mobile_i2c_algorithm;
|
|
adap->dev.parent = &dev->dev;
|
|
adap->retries = 5;
|
|
adap->nr = dev->id;
|
|
adap->dev.of_node = dev->dev.of_node;
|
|
|
|
strlcpy(adap->name, dev->name, sizeof(adap->name));
|
|
|
|
spin_lock_init(&pd->lock);
|
|
init_waitqueue_head(&pd->wait);
|
|
|
|
ret = i2c_add_numbered_adapter(adap);
|
|
if (ret < 0) {
|
|
sh_mobile_i2c_release_dma(pd);
|
|
dev_err(&dev->dev, "cannot add numbered adapter\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_mobile_i2c_remove(struct platform_device *dev)
|
|
{
|
|
struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
|
|
|
|
i2c_del_adapter(&pd->adap);
|
|
sh_mobile_i2c_release_dma(pd);
|
|
pm_runtime_disable(&dev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static int sh_mobile_i2c_runtime_nop(struct device *dev)
|
|
{
|
|
/* Runtime PM callback shared between ->runtime_suspend()
|
|
* and ->runtime_resume(). Simply returns success.
|
|
*
|
|
* This driver re-initializes all registers after
|
|
* pm_runtime_get_sync() anyway so there is no need
|
|
* to save and restore registers here.
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
|
|
.runtime_suspend = sh_mobile_i2c_runtime_nop,
|
|
.runtime_resume = sh_mobile_i2c_runtime_nop,
|
|
};
|
|
|
|
static struct platform_driver sh_mobile_i2c_driver = {
|
|
.driver = {
|
|
.name = "i2c-sh_mobile",
|
|
.pm = &sh_mobile_i2c_dev_pm_ops,
|
|
.of_match_table = sh_mobile_i2c_dt_ids,
|
|
},
|
|
.probe = sh_mobile_i2c_probe,
|
|
.remove = sh_mobile_i2c_remove,
|
|
};
|
|
|
|
static int __init sh_mobile_i2c_adap_init(void)
|
|
{
|
|
return platform_driver_register(&sh_mobile_i2c_driver);
|
|
}
|
|
subsys_initcall(sh_mobile_i2c_adap_init);
|
|
|
|
static void __exit sh_mobile_i2c_adap_exit(void)
|
|
{
|
|
platform_driver_unregister(&sh_mobile_i2c_driver);
|
|
}
|
|
module_exit(sh_mobile_i2c_adap_exit);
|
|
|
|
MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
|
|
MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:i2c-sh_mobile");
|