![Tony Lindgren](/assets/img/avatar_default.png)
Set up function pointers for DMA so get closer to being able to build in all the DMA engines. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
597 lines
16 KiB
C
597 lines
16 KiB
C
/*
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* Texas Instruments DA8xx/OMAP-L1x "glue layer"
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*
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* Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
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*
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* Based on the DaVinci "glue layer" code.
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* Copyright (C) 2005-2006 by Texas Instruments
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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* The Inventra Controller Driver for Linux is distributed in
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* the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with The Inventra Controller Driver for Linux ; if not,
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* write to the Free Software Foundation, Inc., 59 Temple Place,
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* Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb/usb_phy_generic.h>
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#include <mach/da8xx.h>
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#include <linux/platform_data/usb-davinci.h>
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#include "musb_core.h"
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/*
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* DA8XX specific definitions
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*/
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/* USB 2.0 OTG module registers */
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#define DA8XX_USB_REVISION_REG 0x00
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#define DA8XX_USB_CTRL_REG 0x04
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#define DA8XX_USB_STAT_REG 0x08
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#define DA8XX_USB_EMULATION_REG 0x0c
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#define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
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#define DA8XX_USB_AUTOREQ_REG 0x14
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#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
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#define DA8XX_USB_TEARDOWN_REG 0x1c
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#define DA8XX_USB_INTR_SRC_REG 0x20
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#define DA8XX_USB_INTR_SRC_SET_REG 0x24
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#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
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#define DA8XX_USB_INTR_MASK_REG 0x2c
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#define DA8XX_USB_INTR_MASK_SET_REG 0x30
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#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
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#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
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#define DA8XX_USB_END_OF_INTR_REG 0x3c
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#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
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/* Control register bits */
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#define DA8XX_SOFT_RESET_MASK 1
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#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
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#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
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/* USB interrupt register bits */
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#define DA8XX_INTR_USB_SHIFT 16
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#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
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/* interrupts and DRVVBUS interrupt */
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#define DA8XX_INTR_DRVVBUS 0x100
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#define DA8XX_INTR_RX_SHIFT 8
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#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
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#define DA8XX_INTR_TX_SHIFT 0
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#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
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#define DA8XX_MENTOR_CORE_OFFSET 0x400
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#define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
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struct da8xx_glue {
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struct device *dev;
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struct platform_device *musb;
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struct platform_device *phy;
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struct clk *clk;
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};
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/*
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* REVISIT (PM): we should be able to keep the PHY in low power mode most
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* of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
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* and, when in host mode, autosuspending idle root ports... PHY_PLLON
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* (overriding SUSPENDM?) then likely needs to stay off.
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*/
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static inline void phy_on(void)
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{
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u32 cfgchip2 = __raw_readl(CFGCHIP2);
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/*
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* Start the on-chip PHY and its PLL.
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*/
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cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
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cfgchip2 |= CFGCHIP2_PHY_PLLON;
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__raw_writel(cfgchip2, CFGCHIP2);
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pr_info("Waiting for USB PHY clock good...\n");
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while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
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cpu_relax();
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}
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static inline void phy_off(void)
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{
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u32 cfgchip2 = __raw_readl(CFGCHIP2);
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/*
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* Ensure that USB 1.1 reference clock is not being sourced from
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* USB 2.0 PHY. Otherwise do not power down the PHY.
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*/
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if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
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(cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
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pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
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"can't power it down\n");
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return;
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}
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/*
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* Power down the on-chip PHY.
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*/
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cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
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__raw_writel(cfgchip2, CFGCHIP2);
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}
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/*
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* Because we don't set CTRL.UINT, it's "important" to:
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* - not read/write INTRUSB/INTRUSBE (except during
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* initial setup, as a workaround);
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* - use INTSET/INTCLR instead.
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*/
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/**
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* da8xx_musb_enable - enable interrupts
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*/
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static void da8xx_musb_enable(struct musb *musb)
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{
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void __iomem *reg_base = musb->ctrl_base;
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u32 mask;
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/* Workaround: setup IRQs through both register sets. */
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mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
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((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
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DA8XX_INTR_USB_MASK;
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musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
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/* Force the DRVVBUS IRQ so we can start polling for ID change. */
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musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
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DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
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}
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/**
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* da8xx_musb_disable - disable HDRC and flush interrupts
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*/
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static void da8xx_musb_disable(struct musb *musb)
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{
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void __iomem *reg_base = musb->ctrl_base;
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musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
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DA8XX_INTR_USB_MASK |
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DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
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musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
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musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
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}
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#define portstate(stmt) stmt
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static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
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{
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WARN_ON(is_on && is_peripheral_active(musb));
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}
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#define POLL_SECONDS 2
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static struct timer_list otg_workaround;
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static void otg_timer(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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void __iomem *mregs = musb->mregs;
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u8 devctl;
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unsigned long flags;
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/*
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* We poll because DaVinci's won't expose several OTG-critical
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* status change events (from the transceiver) otherwise.
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*/
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
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usb_otg_state_string(musb->xceiv->otg->state));
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv->otg->state) {
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case OTG_STATE_A_WAIT_BCON:
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devctl &= ~MUSB_DEVCTL_SESSION;
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musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
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devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE) {
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musb->xceiv->otg->state = OTG_STATE_B_IDLE;
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MUSB_DEV_MODE(musb);
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} else {
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musb->xceiv->otg->state = OTG_STATE_A_IDLE;
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MUSB_HST_MODE(musb);
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}
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break;
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case OTG_STATE_A_WAIT_VFALL:
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/*
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* Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
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* RTL seems to mis-handle session "start" otherwise (or in
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* our case "recover"), in routine "VBUS was valid by the time
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* VBUSERR got reported during enumeration" cases.
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*/
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if (devctl & MUSB_DEVCTL_VBUS) {
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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break;
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}
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
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musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
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MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
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break;
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case OTG_STATE_B_IDLE:
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/*
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* There's no ID-changed IRQ, so we have no good way to tell
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* when to switch to the A-Default state machine (by setting
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* the DEVCTL.Session bit).
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*
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* Workaround: whenever we're in B_IDLE, try setting the
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* session flag every few seconds. If it works, ID was
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* grounded and we're now in the A-Default state machine.
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*
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* NOTE: setting the session flag is _supposed_ to trigger
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* SRP but clearly it doesn't.
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*/
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musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE)
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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else
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musb->xceiv->otg->state = OTG_STATE_A_IDLE;
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break;
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default:
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
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{
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static unsigned long last_timer;
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if (timeout == 0)
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timeout = jiffies + msecs_to_jiffies(3);
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/* Never idle if active, or when VBUS timeout is not set as host */
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if (musb->is_active || (musb->a_wait_bcon == 0 &&
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musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
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dev_dbg(musb->controller, "%s active, deleting timer\n",
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usb_otg_state_string(musb->xceiv->otg->state));
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del_timer(&otg_workaround);
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last_timer = jiffies;
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return;
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}
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if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
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dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
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return;
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}
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last_timer = timeout;
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dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
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usb_otg_state_string(musb->xceiv->otg->state),
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jiffies_to_msecs(timeout - jiffies));
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mod_timer(&otg_workaround, timeout);
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}
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static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
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{
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struct musb *musb = hci;
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void __iomem *reg_base = musb->ctrl_base;
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struct usb_otg *otg = musb->xceiv->otg;
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unsigned long flags;
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irqreturn_t ret = IRQ_NONE;
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u32 status;
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spin_lock_irqsave(&musb->lock, flags);
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/*
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* NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
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* the Mentor registers (except for setup), use the TI ones and EOI.
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*/
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/* Acknowledge and handle non-CPPI interrupts */
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status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
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if (!status)
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goto eoi;
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musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
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dev_dbg(musb->controller, "USB IRQ %08x\n", status);
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musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
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musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
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musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
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/*
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* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
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* DA8xx's missing ID change IRQ. We need an ID change IRQ to
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* switch appropriately between halves of the OTG state machine.
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* Managing DEVCTL.Session per Mentor docs requires that we know its
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* value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
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* Also, DRVVBUS pulses for SRP (but not at 5 V)...
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*/
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if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
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int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
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void __iomem *mregs = musb->mregs;
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u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
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int err;
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err = musb->int_usb & MUSB_INTR_VBUSERROR;
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if (err) {
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/*
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* The Mentor core doesn't debounce VBUS as needed
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* to cope with device connect current spikes. This
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* means it's not uncommon for bus-powered devices
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* to get VBUS errors during enumeration.
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*
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* This is a workaround, but newer RTL from Mentor
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* seems to allow a better one: "re"-starting sessions
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* without waiting for VBUS to stop registering in
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* devctl.
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*/
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musb->int_usb &= ~MUSB_INTR_VBUSERROR;
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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WARNING("VBUS error workaround (delay coming)\n");
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} else if (drvvbus) {
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MUSB_HST_MODE(musb);
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otg->default_a = 1;
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
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portstate(musb->port1_status |= USB_PORT_STAT_POWER);
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del_timer(&otg_workaround);
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} else {
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musb->is_active = 0;
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MUSB_DEV_MODE(musb);
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otg->default_a = 0;
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musb->xceiv->otg->state = OTG_STATE_B_IDLE;
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portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
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}
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dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
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drvvbus ? "on" : "off",
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usb_otg_state_string(musb->xceiv->otg->state),
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err ? " ERROR" : "",
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devctl);
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ret = IRQ_HANDLED;
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}
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if (musb->int_tx || musb->int_rx || musb->int_usb)
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ret |= musb_interrupt(musb);
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eoi:
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/* EOI needs to be written for the IRQ to be re-asserted. */
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if (ret == IRQ_HANDLED || status)
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musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
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/* Poll for ID change */
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if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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spin_unlock_irqrestore(&musb->lock, flags);
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return ret;
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}
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static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
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{
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u32 cfgchip2 = __raw_readl(CFGCHIP2);
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cfgchip2 &= ~CFGCHIP2_OTGMODE;
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switch (musb_mode) {
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case MUSB_HOST: /* Force VBUS valid, ID = 0 */
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cfgchip2 |= CFGCHIP2_FORCE_HOST;
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break;
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case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
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cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
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break;
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case MUSB_OTG: /* Don't override the VBUS/ID comparators */
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cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
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break;
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default:
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dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
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}
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__raw_writel(cfgchip2, CFGCHIP2);
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return 0;
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}
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static int da8xx_musb_init(struct musb *musb)
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{
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void __iomem *reg_base = musb->ctrl_base;
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u32 rev;
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int ret = -ENODEV;
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musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
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/* Returns zero if e.g. not clocked */
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rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
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if (!rev)
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goto fail;
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musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
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if (IS_ERR_OR_NULL(musb->xceiv)) {
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ret = -EPROBE_DEFER;
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goto fail;
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}
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setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
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/* Reset the controller */
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musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
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/* Start the on-chip PHY and its PLL. */
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phy_on();
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msleep(5);
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/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
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pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
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rev, __raw_readl(CFGCHIP2),
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musb_readb(reg_base, DA8XX_USB_CTRL_REG));
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musb->isr = da8xx_musb_interrupt;
|
|
return 0;
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
static int da8xx_musb_exit(struct musb *musb)
|
|
{
|
|
del_timer_sync(&otg_workaround);
|
|
|
|
phy_off();
|
|
|
|
usb_put_phy(musb->xceiv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct musb_platform_ops da8xx_ops = {
|
|
.quirks = MUSB_DMA_CPPI | MUSB_INDEXED_EP,
|
|
.init = da8xx_musb_init,
|
|
.exit = da8xx_musb_exit,
|
|
|
|
.fifo_mode = 2,
|
|
#ifdef CONFIG_USB_TI_CPPI_DMA
|
|
.dma_init = cppi_dma_controller_create,
|
|
.dma_exit = cppi_dma_controller_destroy,
|
|
#endif
|
|
.enable = da8xx_musb_enable,
|
|
.disable = da8xx_musb_disable,
|
|
|
|
.set_mode = da8xx_musb_set_mode,
|
|
.try_idle = da8xx_musb_try_idle,
|
|
|
|
.set_vbus = da8xx_musb_set_vbus,
|
|
};
|
|
|
|
static const struct platform_device_info da8xx_dev_info = {
|
|
.name = "musb-hdrc",
|
|
.id = PLATFORM_DEVID_AUTO,
|
|
.dma_mask = DMA_BIT_MASK(32),
|
|
};
|
|
|
|
static int da8xx_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource musb_resources[2];
|
|
struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
|
struct platform_device *musb;
|
|
struct da8xx_glue *glue;
|
|
struct platform_device_info pinfo;
|
|
struct clk *clk;
|
|
|
|
int ret = -ENOMEM;
|
|
|
|
glue = kzalloc(sizeof(*glue), GFP_KERNEL);
|
|
if (!glue) {
|
|
dev_err(&pdev->dev, "failed to allocate glue context\n");
|
|
goto err0;
|
|
}
|
|
|
|
clk = clk_get(&pdev->dev, "usb20");
|
|
if (IS_ERR(clk)) {
|
|
dev_err(&pdev->dev, "failed to get clock\n");
|
|
ret = PTR_ERR(clk);
|
|
goto err3;
|
|
}
|
|
|
|
ret = clk_enable(clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to enable clock\n");
|
|
goto err4;
|
|
}
|
|
|
|
glue->dev = &pdev->dev;
|
|
glue->clk = clk;
|
|
|
|
pdata->platform_ops = &da8xx_ops;
|
|
|
|
glue->phy = usb_phy_generic_register();
|
|
if (IS_ERR(glue->phy)) {
|
|
ret = PTR_ERR(glue->phy);
|
|
goto err5;
|
|
}
|
|
platform_set_drvdata(pdev, glue);
|
|
|
|
memset(musb_resources, 0x00, sizeof(*musb_resources) *
|
|
ARRAY_SIZE(musb_resources));
|
|
|
|
musb_resources[0].name = pdev->resource[0].name;
|
|
musb_resources[0].start = pdev->resource[0].start;
|
|
musb_resources[0].end = pdev->resource[0].end;
|
|
musb_resources[0].flags = pdev->resource[0].flags;
|
|
|
|
musb_resources[1].name = pdev->resource[1].name;
|
|
musb_resources[1].start = pdev->resource[1].start;
|
|
musb_resources[1].end = pdev->resource[1].end;
|
|
musb_resources[1].flags = pdev->resource[1].flags;
|
|
|
|
pinfo = da8xx_dev_info;
|
|
pinfo.parent = &pdev->dev;
|
|
pinfo.res = musb_resources;
|
|
pinfo.num_res = ARRAY_SIZE(musb_resources);
|
|
pinfo.data = pdata;
|
|
pinfo.size_data = sizeof(*pdata);
|
|
|
|
glue->musb = musb = platform_device_register_full(&pinfo);
|
|
if (IS_ERR(musb)) {
|
|
ret = PTR_ERR(musb);
|
|
dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
|
|
goto err6;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err6:
|
|
usb_phy_generic_unregister(glue->phy);
|
|
|
|
err5:
|
|
clk_disable(clk);
|
|
|
|
err4:
|
|
clk_put(clk);
|
|
|
|
err3:
|
|
kfree(glue);
|
|
|
|
err0:
|
|
return ret;
|
|
}
|
|
|
|
static int da8xx_remove(struct platform_device *pdev)
|
|
{
|
|
struct da8xx_glue *glue = platform_get_drvdata(pdev);
|
|
|
|
platform_device_unregister(glue->musb);
|
|
usb_phy_generic_unregister(glue->phy);
|
|
clk_disable(glue->clk);
|
|
clk_put(glue->clk);
|
|
kfree(glue);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver da8xx_driver = {
|
|
.probe = da8xx_probe,
|
|
.remove = da8xx_remove,
|
|
.driver = {
|
|
.name = "musb-da8xx",
|
|
},
|
|
};
|
|
|
|
MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
|
|
MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
module_platform_driver(da8xx_driver);
|