72838a1703
This patch checks if the watchdog enable bit is set in the DCL register meaning that the hardware watchdog actually works and if so, register the ar7_wdt platform_device. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
182 lines
4.4 KiB
C
182 lines
4.4 KiB
C
/*
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* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __AR7_H__
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#define __AR7_H__
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <asm/addrspace.h>
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#define AR7_SDRAM_BASE 0x14000000
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#define AR7_REGS_BASE 0x08610000
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#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
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#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
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/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
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#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
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#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
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#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
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#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
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#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
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#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
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#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
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#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
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#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
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#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
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#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
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#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
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#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
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#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
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#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
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#define AR7_RESET_PEREPHERIAL 0x0
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#define AR7_RESET_SOFTWARE 0x4
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#define AR7_RESET_STATUS 0x8
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#define AR7_RESET_BIT_CPMAC_LO 17
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#define AR7_RESET_BIT_CPMAC_HI 21
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#define AR7_RESET_BIT_MDIO 22
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#define AR7_RESET_BIT_EPHY 26
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/* GPIO control registers */
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#define AR7_GPIO_INPUT 0x0
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#define AR7_GPIO_OUTPUT 0x4
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#define AR7_GPIO_DIR 0x8
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#define AR7_GPIO_ENABLE 0xc
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#define AR7_CHIP_7100 0x18
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#define AR7_CHIP_7200 0x2b
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#define AR7_CHIP_7300 0x05
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/* Interrupts */
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#define AR7_IRQ_UART0 15
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#define AR7_IRQ_UART1 16
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/* Clocks */
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#define AR7_AFE_CLOCK 35328000
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#define AR7_REF_CLOCK 25000000
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#define AR7_XTAL_CLOCK 24000000
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/* DCL */
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#define AR7_WDT_HW_ENA 0x10
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struct plat_cpmac_data {
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int reset_bit;
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int power_bit;
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u32 phy_mask;
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char dev_addr[6];
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};
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struct plat_dsl_data {
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int reset_bit_dsl;
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int reset_bit_sar;
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};
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extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
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static inline u16 ar7_chip_id(void)
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{
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return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
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}
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static inline u8 ar7_chip_rev(void)
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{
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return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
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}
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static inline int ar7_cpu_freq(void)
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{
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return ar7_cpu_clock;
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}
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static inline int ar7_bus_freq(void)
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{
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return ar7_bus_clock;
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}
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static inline int ar7_vbus_freq(void)
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{
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return ar7_bus_clock / 2;
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}
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#define ar7_cpmac_freq ar7_vbus_freq
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static inline int ar7_dsp_freq(void)
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{
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return ar7_dsp_clock;
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}
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static inline int ar7_has_high_cpmac(void)
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{
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u16 chip_id = ar7_chip_id();
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switch (chip_id) {
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case AR7_CHIP_7100:
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case AR7_CHIP_7200:
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return 0;
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case AR7_CHIP_7300:
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return 1;
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default:
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return -ENXIO;
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}
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}
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#define ar7_has_high_vlynq ar7_has_high_cpmac
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#define ar7_has_second_uart ar7_has_high_cpmac
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static inline void ar7_device_enable(u32 bit)
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{
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void *reset_reg =
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(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
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writel(readl(reset_reg) | (1 << bit), reset_reg);
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msleep(20);
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}
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static inline void ar7_device_disable(u32 bit)
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{
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void *reset_reg =
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(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
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writel(readl(reset_reg) & ~(1 << bit), reset_reg);
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msleep(20);
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}
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static inline void ar7_device_reset(u32 bit)
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{
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ar7_device_disable(bit);
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ar7_device_enable(bit);
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}
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static inline void ar7_device_on(u32 bit)
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{
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void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
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writel(readl(power_reg) | (1 << bit), power_reg);
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msleep(20);
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}
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static inline void ar7_device_off(u32 bit)
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{
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void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
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writel(readl(power_reg) & ~(1 << bit), power_reg);
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msleep(20);
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}
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#endif /* __AR7_H__ */
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