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Linus Torvalds d70b1e06eb Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rkuo/linux-hexagon-kernel
Pull Hexagon fixes from Richard Kuo:
 "Changes for the Hexagon architecture (and one touching OpenRISC).

  They include various fixes to make use of additional arch features and
  cleanups.  The largest functional change is a cleanup of the signal
  and event return paths"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rkuo/linux-hexagon-kernel: (32 commits)
  Hexagon: add v4 CS regs to core copyout macro
  Hexagon: use correct translation for VMALLOC_START
  Hexagon: use correct translations for DMA mappings
  Hexagon: fix return value for notify_resume case in do_work_pending
  Hexagon: fix signal number for user mem faults
  Hexagon: remove two Kconfig entries
  arch: remove CONFIG_GENERIC_FIND_NEXT_BIT again
  Hexagon: update copyright dates
  Hexagon: add translation types for __vmnewmap
  Hexagon: fix signal.c compile error
  Hexagon: break up user fn/arg register setting
  Hexagon: use generic sys_fork, sys_vfork, and sys_clone
  Hexagon: fix psp/sp macro
  Hexagon: fix up int enable/disable at ret_from_fork
  Hexagon: add IOMEM and _relaxed IO macros
  Hexagon: switch to using the device type for IO mappings
  Hexagon: don't print info for offline CPU's
  Hexagon: add support for single-stepping (v4+)
  Hexagon: use correct work mask when checking for more work
  Hexagon: add support for additional exceptions
  ...
2013-05-01 07:43:05 -07:00
..
boot/dts openrisc: use new common dtc rule 2012-12-03 17:17:48 -06:00
configs OpenRISC: Build infrastructure 2011-07-22 18:46:30 +02:00
include arch: Consolidate tsk_is_polling() 2013-04-08 17:39:22 +02:00
kernel dump_stack: unify debug information printed by show_regs() 2013-04-30 17:04:02 -07:00
lib ARCH: drivers remove __dev* attributes. 2013-01-03 15:57:13 -08:00
mm mm/openrisc: use common help functions to free reserved pages 2013-04-29 15:54:30 -07:00
Kconfig arch: remove CONFIG_GENERIC_FIND_NEXT_BIT again 2013-04-30 19:40:27 -05:00
Makefile openrisc: use new common dtc rule 2012-12-03 17:17:48 -06:00
README.openrisc OpenRISC: Miscellaneous 2011-07-22 18:46:41 +02:00
TODO.openrisc OpenRISC: Miscellaneous 2011-07-22 18:46:41 +02:00

README.openrisc

OpenRISC Linux
==============

This is a port of Linux to the OpenRISC class of microprocessors; the initial
target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).

For information about OpenRISC processors and ongoing development:

	website		http://openrisc.net

For more information about Linux on OpenRISC, please contact South Pole AB.

	email:		info@southpole.se

	website:	http://southpole.se
			http://southpoleconsulting.com

---------------------------------------------------------------------

Build instructions for OpenRISC toolchain and Linux
===================================================

In order to build and run Linux for OpenRISC, you'll need at least a basic
toolchain and, perhaps, the architectural simulator.  Steps to get these bits
in place are outlined here.

1)  The toolchain can be obtained from openrisc.net.  Instructions for building
a toolchain can be found at:

http://openrisc.net/toolchain-build.html

2) or1ksim (optional)

or1ksim is the architectural simulator which will allow you to actually run
your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.

	git clone git://openrisc.net/jonas/or1ksim-svn

	cd or1ksim
	./configure --prefix=$OPENRISC_PREFIX
	make
	make install

3)  Linux kernel

Build the kernel as usual

	make ARCH=openrisc defconfig
	make ARCH=openrisc

4)  Run in architectural simulator

Grab the or1ksim platform configuration file (from the or1ksim source) and
together with your freshly built vmlinux, run your kernel with the following
incantation:

	sim -f arch/openrisc/or1ksim.cfg vmlinux

---------------------------------------------------------------------

Terminology
===========

In the code, the following particles are used on symbols to limit the scope
to more or less specific processor implementations:

openrisc: the OpenRISC class of processors
or1k:     the OpenRISC 1000 family of processors
or1200:   the OpenRISC 1200 processor

---------------------------------------------------------------------

History
========

18. 11. 2003	Matjaz Breskvar (phoenix@bsemi.com)
	initial port of linux to OpenRISC/or32 architecture.
        all the core stuff is implemented and seams usable.

08. 12. 2003	Matjaz Breskvar (phoenix@bsemi.com)
	complete change of TLB miss handling.
	rewrite of exceptions handling.
	fully functional sash-3.6 in default initrd.
	a much improved version with changes all around.

10. 04. 2004	Matjaz Breskvar (phoenix@bsemi.com)
	alot of bugfixes all over.
	ethernet support, functional http and telnet servers.
	running many standard linux apps.

26. 06. 2004	Matjaz Breskvar (phoenix@bsemi.com)
	port to 2.6.x

30. 11. 2004	Matjaz Breskvar (phoenix@bsemi.com)
	lots of bugfixes and enhancments.
	added opencores framebuffer driver.

09. 10. 2010    Jonas Bonn (jonas@southpole.se)
	major rewrite to bring up to par with upstream Linux 2.6.36