![Jonathan Cameron](/assets/img/avatar_default.png)
The equivalent of both of these are now done via macro magic when the relevant register calls are made. The actual structure elements will shortly go away. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
602 lines
14 KiB
C
602 lines
14 KiB
C
/*
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* Driver for the Nuvoton NAU7802 ADC
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*
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* Copyright 2013 Free Electrons
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*
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* Licensed under the GPLv2 or later.
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*/
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/wait.h>
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#include <linux/log2.h>
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#include <linux/of.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#define NAU7802_REG_PUCTRL 0x00
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#define NAU7802_PUCTRL_RR(x) (x << 0)
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#define NAU7802_PUCTRL_RR_BIT NAU7802_PUCTRL_RR(1)
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#define NAU7802_PUCTRL_PUD(x) (x << 1)
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#define NAU7802_PUCTRL_PUD_BIT NAU7802_PUCTRL_PUD(1)
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#define NAU7802_PUCTRL_PUA(x) (x << 2)
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#define NAU7802_PUCTRL_PUA_BIT NAU7802_PUCTRL_PUA(1)
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#define NAU7802_PUCTRL_PUR(x) (x << 3)
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#define NAU7802_PUCTRL_PUR_BIT NAU7802_PUCTRL_PUR(1)
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#define NAU7802_PUCTRL_CS(x) (x << 4)
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#define NAU7802_PUCTRL_CS_BIT NAU7802_PUCTRL_CS(1)
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#define NAU7802_PUCTRL_CR(x) (x << 5)
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#define NAU7802_PUCTRL_CR_BIT NAU7802_PUCTRL_CR(1)
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#define NAU7802_PUCTRL_AVDDS(x) (x << 7)
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#define NAU7802_PUCTRL_AVDDS_BIT NAU7802_PUCTRL_AVDDS(1)
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#define NAU7802_REG_CTRL1 0x01
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#define NAU7802_CTRL1_VLDO(x) (x << 3)
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#define NAU7802_CTRL1_GAINS(x) (x)
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#define NAU7802_CTRL1_GAINS_BITS 0x07
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#define NAU7802_REG_CTRL2 0x02
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#define NAU7802_CTRL2_CHS(x) (x << 7)
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#define NAU7802_CTRL2_CRS(x) (x << 4)
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#define NAU7802_SAMP_FREQ_320 0x07
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#define NAU7802_CTRL2_CHS_BIT NAU7802_CTRL2_CHS(1)
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#define NAU7802_REG_ADC_B2 0x12
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#define NAU7802_REG_ADC_B1 0x13
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#define NAU7802_REG_ADC_B0 0x14
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#define NAU7802_REG_ADC_CTRL 0x15
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#define NAU7802_MIN_CONVERSIONS 6
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struct nau7802_state {
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struct i2c_client *client;
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s32 last_value;
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struct mutex lock;
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struct mutex data_lock;
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u32 vref_mv;
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u32 conversion_count;
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u32 min_conversions;
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u8 sample_rate;
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u32 scale_avail[8];
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struct completion value_ok;
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};
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#define NAU7802_CHANNEL(chan) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (chan), \
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.scan_index = (chan), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ) \
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}
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static const struct iio_chan_spec nau7802_chan_array[] = {
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NAU7802_CHANNEL(0),
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NAU7802_CHANNEL(1),
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};
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static const u16 nau7802_sample_freq_avail[] = {10, 20, 40, 80,
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10, 10, 10, 320};
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static ssize_t nau7802_show_scales(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct nau7802_state *st = iio_priv(dev_to_iio_dev(dev));
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int i, len = 0;
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for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
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len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09d ",
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st->scale_avail[i]);
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buf[len-1] = '\n';
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return len;
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}
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static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 40 80 320");
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static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, nau7802_show_scales,
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NULL, 0);
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static struct attribute *nau7802_attributes[] = {
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&iio_const_attr_sampling_frequency_available.dev_attr.attr,
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&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
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NULL
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};
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static const struct attribute_group nau7802_attribute_group = {
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.attrs = nau7802_attributes,
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};
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static int nau7802_set_gain(struct nau7802_state *st, int gain)
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{
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int ret;
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mutex_lock(&st->lock);
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st->conversion_count = 0;
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ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
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if (ret < 0)
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goto nau7802_sysfs_set_gain_out;
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ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
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(ret & (~NAU7802_CTRL1_GAINS_BITS)) |
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gain);
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nau7802_sysfs_set_gain_out:
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mutex_unlock(&st->lock);
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return ret;
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}
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static int nau7802_read_conversion(struct nau7802_state *st)
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{
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int data;
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mutex_lock(&st->data_lock);
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data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B2);
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if (data < 0)
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goto nau7802_read_conversion_out;
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st->last_value = data << 16;
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data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B1);
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if (data < 0)
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goto nau7802_read_conversion_out;
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st->last_value |= data << 8;
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data = i2c_smbus_read_byte_data(st->client, NAU7802_REG_ADC_B0);
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if (data < 0)
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goto nau7802_read_conversion_out;
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st->last_value |= data;
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st->last_value = sign_extend32(st->last_value, 23);
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nau7802_read_conversion_out:
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mutex_unlock(&st->data_lock);
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return data;
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}
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/*
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* Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
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*/
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static int nau7802_sync(struct nau7802_state *st)
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{
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int ret;
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ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
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if (ret < 0)
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return ret;
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ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
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ret | NAU7802_PUCTRL_CS_BIT);
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return ret;
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}
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static irqreturn_t nau7802_eoc_trigger(int irq, void *private)
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{
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struct iio_dev *indio_dev = private;
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struct nau7802_state *st = iio_priv(indio_dev);
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int status;
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status = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
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if (status < 0)
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return IRQ_HANDLED;
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if (!(status & NAU7802_PUCTRL_CR_BIT))
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return IRQ_NONE;
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if (nau7802_read_conversion(st) < 0)
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return IRQ_HANDLED;
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/*
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* Because there is actually only one ADC for both channels, we have to
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* wait for enough conversions to happen before getting a significant
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* value when changing channels and the values are far apart.
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*/
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if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
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st->conversion_count++;
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if (st->conversion_count >= NAU7802_MIN_CONVERSIONS)
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complete(&st->value_ok);
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return IRQ_HANDLED;
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}
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static int nau7802_read_irq(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val)
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{
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struct nau7802_state *st = iio_priv(indio_dev);
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int ret;
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reinit_completion(&st->value_ok);
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enable_irq(st->client->irq);
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nau7802_sync(st);
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/* read registers to ensure we flush everything */
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ret = nau7802_read_conversion(st);
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if (ret < 0)
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goto read_chan_info_failure;
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/* Wait for a conversion to finish */
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ret = wait_for_completion_interruptible_timeout(&st->value_ok,
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msecs_to_jiffies(1000));
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if (ret == 0)
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ret = -ETIMEDOUT;
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if (ret < 0)
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goto read_chan_info_failure;
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disable_irq(st->client->irq);
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*val = st->last_value;
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return IIO_VAL_INT;
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read_chan_info_failure:
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disable_irq(st->client->irq);
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return ret;
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}
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static int nau7802_read_poll(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val)
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{
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struct nau7802_state *st = iio_priv(indio_dev);
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int ret;
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nau7802_sync(st);
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/* read registers to ensure we flush everything */
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ret = nau7802_read_conversion(st);
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if (ret < 0)
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return ret;
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/*
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* Because there is actually only one ADC for both channels, we have to
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* wait for enough conversions to happen before getting a significant
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* value when changing channels and the values are far appart.
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*/
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do {
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ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
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if (ret < 0)
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return ret;
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while (!(ret & NAU7802_PUCTRL_CR_BIT)) {
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if (st->sample_rate != NAU7802_SAMP_FREQ_320)
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msleep(20);
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else
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mdelay(4);
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ret = i2c_smbus_read_byte_data(st->client,
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NAU7802_REG_PUCTRL);
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if (ret < 0)
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return ret;
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}
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ret = nau7802_read_conversion(st);
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if (ret < 0)
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return ret;
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if (st->conversion_count < NAU7802_MIN_CONVERSIONS)
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st->conversion_count++;
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} while (st->conversion_count < NAU7802_MIN_CONVERSIONS);
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*val = st->last_value;
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return IIO_VAL_INT;
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}
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static int nau7802_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct nau7802_state *st = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&st->lock);
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/*
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* Select the channel to use
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* - Channel 1 is value 0 in the CHS register
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* - Channel 2 is value 1 in the CHS register
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*/
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ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL2);
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if (ret < 0) {
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mutex_unlock(&st->lock);
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return ret;
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}
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if (((ret & NAU7802_CTRL2_CHS_BIT) && !chan->channel) ||
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(!(ret & NAU7802_CTRL2_CHS_BIT) &&
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chan->channel)) {
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st->conversion_count = 0;
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ret = i2c_smbus_write_byte_data(st->client,
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NAU7802_REG_CTRL2,
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NAU7802_CTRL2_CHS(chan->channel) |
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NAU7802_CTRL2_CRS(st->sample_rate));
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if (ret < 0) {
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mutex_unlock(&st->lock);
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return ret;
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}
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}
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if (st->client->irq)
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ret = nau7802_read_irq(indio_dev, chan, val);
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else
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ret = nau7802_read_poll(indio_dev, chan, val);
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mutex_unlock(&st->lock);
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return ret;
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case IIO_CHAN_INFO_SCALE:
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ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_CTRL1);
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if (ret < 0)
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return ret;
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/*
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* We have 24 bits of signed data, that means 23 bits of data
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* plus the sign bit
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*/
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*val = st->vref_mv;
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*val2 = 23 + (ret & NAU7802_CTRL1_GAINS_BITS);
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = nau7802_sample_freq_avail[st->sample_rate];
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*val2 = 0;
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return IIO_VAL_INT;
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default:
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break;
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}
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return -EINVAL;
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}
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static int nau7802_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct nau7802_state *st = iio_priv(indio_dev);
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int i, ret;
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switch (mask) {
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case IIO_CHAN_INFO_SCALE:
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for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
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if (val2 == st->scale_avail[i])
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return nau7802_set_gain(st, i);
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break;
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case IIO_CHAN_INFO_SAMP_FREQ:
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for (i = 0; i < ARRAY_SIZE(nau7802_sample_freq_avail); i++)
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if (val == nau7802_sample_freq_avail[i]) {
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mutex_lock(&st->lock);
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st->sample_rate = i;
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st->conversion_count = 0;
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ret = i2c_smbus_write_byte_data(st->client,
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NAU7802_REG_CTRL2,
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NAU7802_CTRL2_CRS(st->sample_rate));
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mutex_unlock(&st->lock);
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return ret;
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}
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break;
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default:
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break;
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}
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return -EINVAL;
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}
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static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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long mask)
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{
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return IIO_VAL_INT_PLUS_NANO;
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}
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static const struct iio_info nau7802_info = {
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.read_raw = &nau7802_read_raw,
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.write_raw = &nau7802_write_raw,
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.write_raw_get_fmt = nau7802_write_raw_get_fmt,
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.attrs = &nau7802_attribute_group,
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};
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static int nau7802_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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struct iio_dev *indio_dev;
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struct nau7802_state *st;
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struct device_node *np = client->dev.of_node;
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int i, ret;
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u8 data;
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u32 tmp = 0;
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if (!client->dev.of_node) {
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dev_err(&client->dev, "No device tree node available.\n");
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return -EINVAL;
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}
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indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
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if (indio_dev == NULL)
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return -ENOMEM;
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st = iio_priv(indio_dev);
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i2c_set_clientdata(client, indio_dev);
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indio_dev->dev.parent = &client->dev;
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indio_dev->dev.of_node = client->dev.of_node;
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indio_dev->name = dev_name(&client->dev);
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->info = &nau7802_info;
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st->client = client;
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/* Reset the device */
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ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
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NAU7802_PUCTRL_RR_BIT);
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if (ret < 0)
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return ret;
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/* Enter normal operation mode */
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ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL,
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NAU7802_PUCTRL_PUD_BIT);
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if (ret < 0)
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return ret;
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/*
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* After about 200 usecs, the device should be ready and then
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* the Power Up bit will be set to 1. If not, wait for it.
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*/
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udelay(210);
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ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);
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if (ret < 0)
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return ret;
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if (!(ret & NAU7802_PUCTRL_PUR_BIT))
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return ret;
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of_property_read_u32(np, "nuvoton,vldo", &tmp);
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st->vref_mv = tmp;
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data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT |
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NAU7802_PUCTRL_CS_BIT;
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if (tmp >= 2400)
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data |= NAU7802_PUCTRL_AVDDS_BIT;
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ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_PUCTRL, data);
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if (ret < 0)
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return ret;
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ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_ADC_CTRL, 0x30);
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if (ret < 0)
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return ret;
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if (tmp >= 2400) {
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data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
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ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL1,
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data);
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if (ret < 0)
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return ret;
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}
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/* Populate available ADC input ranges */
|
|
for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
|
|
st->scale_avail[i] = (((u64)st->vref_mv) * 1000000000ULL)
|
|
>> (23 + i);
|
|
|
|
init_completion(&st->value_ok);
|
|
|
|
/*
|
|
* The ADC fires continuously and we can't do anything about
|
|
* it. So we need to have the IRQ disabled by default, and we
|
|
* will enable them back when we will need them..
|
|
*/
|
|
if (client->irq) {
|
|
ret = request_threaded_irq(client->irq,
|
|
NULL,
|
|
nau7802_eoc_trigger,
|
|
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
|
|
client->dev.driver->name,
|
|
indio_dev);
|
|
if (ret) {
|
|
/*
|
|
* What may happen here is that our IRQ controller is
|
|
* not able to get level interrupt but this is required
|
|
* by this ADC as when going over 40 sample per second,
|
|
* the interrupt line may stay high between conversions.
|
|
* So, we continue no matter what but we switch to
|
|
* polling mode.
|
|
*/
|
|
dev_info(&client->dev,
|
|
"Failed to allocate IRQ, using polling mode\n");
|
|
client->irq = 0;
|
|
} else
|
|
disable_irq(client->irq);
|
|
}
|
|
|
|
if (!client->irq) {
|
|
/*
|
|
* We are polling, use the fastest sample rate by
|
|
* default
|
|
*/
|
|
st->sample_rate = NAU7802_SAMP_FREQ_320;
|
|
ret = i2c_smbus_write_byte_data(st->client, NAU7802_REG_CTRL2,
|
|
NAU7802_CTRL2_CRS(st->sample_rate));
|
|
if (ret)
|
|
goto error_free_irq;
|
|
}
|
|
|
|
/* Setup the ADC channels available on the board */
|
|
indio_dev->num_channels = ARRAY_SIZE(nau7802_chan_array);
|
|
indio_dev->channels = nau7802_chan_array;
|
|
|
|
mutex_init(&st->lock);
|
|
mutex_init(&st->data_lock);
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret < 0) {
|
|
dev_err(&client->dev, "Couldn't register the device.\n");
|
|
goto error_device_register;
|
|
}
|
|
|
|
return 0;
|
|
|
|
error_device_register:
|
|
mutex_destroy(&st->lock);
|
|
mutex_destroy(&st->data_lock);
|
|
error_free_irq:
|
|
if (client->irq)
|
|
free_irq(client->irq, indio_dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int nau7802_remove(struct i2c_client *client)
|
|
{
|
|
struct iio_dev *indio_dev = i2c_get_clientdata(client);
|
|
struct nau7802_state *st = iio_priv(indio_dev);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
mutex_destroy(&st->lock);
|
|
mutex_destroy(&st->data_lock);
|
|
if (client->irq)
|
|
free_irq(client->irq, indio_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct i2c_device_id nau7802_i2c_id[] = {
|
|
{ "nau7802", 0 },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(i2c, nau7802_i2c_id);
|
|
|
|
static const struct of_device_id nau7802_dt_ids[] = {
|
|
{ .compatible = "nuvoton,nau7802" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, nau7802_dt_ids);
|
|
|
|
static struct i2c_driver nau7802_driver = {
|
|
.probe = nau7802_probe,
|
|
.remove = nau7802_remove,
|
|
.id_table = nau7802_i2c_id,
|
|
.driver = {
|
|
.name = "nau7802",
|
|
.of_match_table = nau7802_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_i2c_driver(nau7802_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Nuvoton NAU7802 ADC Driver");
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|
|
MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
|