![Greg Kroah-Hartman](/assets/img/avatar_default.png)
Now that the SPDX tag is in all USB files, that identifies the license in a specific and legally-defined manner. So the extra GPL text wording can be removed as it is no longer needed at all. This is done on a quest to remove the 700+ different ways that files in the kernel describe the GPL license text. And there's unneeded stuff like the address (sometimes incorrect) for the FSF which is never needed. No copyright headers or other non-license-description text was removed. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
397 lines
11 KiB
C
397 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* drivers/usb/musb/ux500_dma.c
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*
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* U8500 DMA support code
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*
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* Copyright (C) 2009 STMicroelectronics
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* Copyright (C) 2011 ST-Ericsson SA
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* Authors:
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* Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
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* Praveena Nadahally <praveen.nadahally@stericsson.com>
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* Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/pfn.h>
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#include <linux/sizes.h>
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#include <linux/platform_data/usb-musb-ux500.h>
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#include "musb_core.h"
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static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
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"iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
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static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
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"oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
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struct ux500_dma_channel {
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struct dma_channel channel;
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struct ux500_dma_controller *controller;
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struct musb_hw_ep *hw_ep;
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struct dma_chan *dma_chan;
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unsigned int cur_len;
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dma_cookie_t cookie;
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u8 ch_num;
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u8 is_tx;
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u8 is_allocated;
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};
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struct ux500_dma_controller {
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struct dma_controller controller;
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struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
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struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
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void *private_data;
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dma_addr_t phy_base;
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};
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/* Work function invoked from DMA callback to handle rx transfers. */
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static void ux500_dma_callback(void *private_data)
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{
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struct dma_channel *channel = private_data;
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struct ux500_dma_channel *ux500_channel = channel->private_data;
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struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
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struct musb *musb = hw_ep->musb;
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unsigned long flags;
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dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
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hw_ep->epnum);
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spin_lock_irqsave(&musb->lock, flags);
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ux500_channel->channel.actual_len = ux500_channel->cur_len;
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ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
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musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx);
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static bool ux500_configure_channel(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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struct ux500_dma_channel *ux500_channel = channel->private_data;
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struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
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struct dma_chan *dma_chan = ux500_channel->dma_chan;
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struct dma_async_tx_descriptor *dma_desc;
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enum dma_transfer_direction direction;
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struct scatterlist sg;
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struct dma_slave_config slave_conf;
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enum dma_slave_buswidth addr_width;
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struct musb *musb = ux500_channel->controller->private_data;
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dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) +
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ux500_channel->controller->phy_base);
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dev_dbg(musb->controller,
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"packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
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packet_sz, mode, (unsigned long long) dma_addr,
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len, ux500_channel->is_tx);
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ux500_channel->cur_len = len;
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sg_init_table(&sg, 1);
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sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
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offset_in_page(dma_addr));
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sg_dma_address(&sg) = dma_addr;
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sg_dma_len(&sg) = len;
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direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
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addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
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DMA_SLAVE_BUSWIDTH_4_BYTES;
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slave_conf.direction = direction;
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slave_conf.src_addr = usb_fifo_addr;
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slave_conf.src_addr_width = addr_width;
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slave_conf.src_maxburst = 16;
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slave_conf.dst_addr = usb_fifo_addr;
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slave_conf.dst_addr_width = addr_width;
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slave_conf.dst_maxburst = 16;
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slave_conf.device_fc = false;
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dmaengine_slave_config(dma_chan, &slave_conf);
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dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma_desc)
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return false;
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dma_desc->callback = ux500_dma_callback;
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dma_desc->callback_param = channel;
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ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
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dma_async_issue_pending(dma_chan);
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return true;
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}
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static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
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struct musb_hw_ep *hw_ep, u8 is_tx)
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{
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struct ux500_dma_controller *controller = container_of(c,
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struct ux500_dma_controller, controller);
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struct ux500_dma_channel *ux500_channel = NULL;
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struct musb *musb = controller->private_data;
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u8 ch_num = hw_ep->epnum - 1;
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/* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
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* to specified hw_ep. For example DMA channel 0 can only be allocated
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* to hw_ep 1 and 9.
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*/
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if (ch_num > 7)
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ch_num -= 8;
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if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
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return NULL;
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ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
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&(controller->rx_channel[ch_num]) ;
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/* Check if channel is already used. */
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if (ux500_channel->is_allocated)
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return NULL;
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ux500_channel->hw_ep = hw_ep;
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ux500_channel->is_allocated = 1;
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dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
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hw_ep->epnum, is_tx, ch_num);
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return &(ux500_channel->channel);
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}
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static void ux500_dma_channel_release(struct dma_channel *channel)
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{
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struct ux500_dma_channel *ux500_channel = channel->private_data;
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struct musb *musb = ux500_channel->controller->private_data;
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dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
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if (ux500_channel->is_allocated) {
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ux500_channel->is_allocated = 0;
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channel->status = MUSB_DMA_STATUS_FREE;
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channel->actual_len = 0;
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}
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}
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static int ux500_dma_is_compatible(struct dma_channel *channel,
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u16 maxpacket, void *buf, u32 length)
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{
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if ((maxpacket & 0x3) ||
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((unsigned long int) buf & 0x3) ||
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(length < 512) ||
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(length & 0x3))
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return false;
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else
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return true;
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}
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static int ux500_dma_channel_program(struct dma_channel *channel,
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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int ret;
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BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
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channel->status == MUSB_DMA_STATUS_BUSY);
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channel->status = MUSB_DMA_STATUS_BUSY;
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channel->actual_len = 0;
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ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
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if (!ret)
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channel->status = MUSB_DMA_STATUS_FREE;
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return ret;
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}
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static int ux500_dma_channel_abort(struct dma_channel *channel)
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{
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struct ux500_dma_channel *ux500_channel = channel->private_data;
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struct ux500_dma_controller *controller = ux500_channel->controller;
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struct musb *musb = controller->private_data;
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void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
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u16 csr;
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dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
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ux500_channel->ch_num, ux500_channel->is_tx);
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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if (ux500_channel->is_tx) {
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csr = musb_readw(epio, MUSB_TXCSR);
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csr &= ~(MUSB_TXCSR_AUTOSET |
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MUSB_TXCSR_DMAENAB |
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MUSB_TXCSR_DMAMODE);
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musb_writew(epio, MUSB_TXCSR, csr);
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} else {
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csr = musb_readw(epio, MUSB_RXCSR);
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csr &= ~(MUSB_RXCSR_AUTOCLEAR |
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MUSB_RXCSR_DMAENAB |
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MUSB_RXCSR_DMAMODE);
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musb_writew(epio, MUSB_RXCSR, csr);
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}
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dmaengine_terminate_all(ux500_channel->dma_chan);
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channel->status = MUSB_DMA_STATUS_FREE;
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}
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return 0;
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}
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static void ux500_dma_controller_stop(struct ux500_dma_controller *controller)
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{
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struct ux500_dma_channel *ux500_channel;
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struct dma_channel *channel;
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u8 ch_num;
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for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
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channel = &controller->rx_channel[ch_num].channel;
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ux500_channel = channel->private_data;
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ux500_dma_channel_release(channel);
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if (ux500_channel->dma_chan)
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dma_release_channel(ux500_channel->dma_chan);
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}
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for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
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channel = &controller->tx_channel[ch_num].channel;
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ux500_channel = channel->private_data;
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ux500_dma_channel_release(channel);
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if (ux500_channel->dma_chan)
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dma_release_channel(ux500_channel->dma_chan);
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}
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}
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static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
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{
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struct ux500_dma_channel *ux500_channel = NULL;
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struct musb *musb = controller->private_data;
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struct device *dev = musb->controller;
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struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
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struct ux500_musb_board_data *data;
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struct dma_channel *dma_channel = NULL;
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char **chan_names;
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u32 ch_num;
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u8 dir;
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u8 is_tx = 0;
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void **param_array;
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struct ux500_dma_channel *channel_array;
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dma_cap_mask_t mask;
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if (!plat) {
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dev_err(musb->controller, "No platform data\n");
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return -EINVAL;
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}
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data = plat->board_data;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/* Prepare the loop for RX channels */
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channel_array = controller->rx_channel;
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param_array = data ? data->dma_rx_param_array : NULL;
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chan_names = (char **)iep_chan_names;
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for (dir = 0; dir < 2; dir++) {
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for (ch_num = 0;
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ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
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ch_num++) {
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ux500_channel = &channel_array[ch_num];
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ux500_channel->controller = controller;
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ux500_channel->ch_num = ch_num;
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ux500_channel->is_tx = is_tx;
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dma_channel = &(ux500_channel->channel);
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dma_channel->private_data = ux500_channel;
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dma_channel->status = MUSB_DMA_STATUS_FREE;
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dma_channel->max_len = SZ_16M;
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ux500_channel->dma_chan =
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dma_request_slave_channel(dev, chan_names[ch_num]);
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if (!ux500_channel->dma_chan)
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ux500_channel->dma_chan =
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dma_request_channel(mask,
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data ?
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data->dma_filter :
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NULL,
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param_array ?
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param_array[ch_num] :
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NULL);
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if (!ux500_channel->dma_chan) {
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ERR("Dma pipe allocation error dir=%d ch=%d\n",
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dir, ch_num);
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/* Release already allocated channels */
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ux500_dma_controller_stop(controller);
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return -EBUSY;
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}
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}
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/* Prepare the loop for TX channels */
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channel_array = controller->tx_channel;
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param_array = data ? data->dma_tx_param_array : NULL;
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chan_names = (char **)oep_chan_names;
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is_tx = 1;
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}
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return 0;
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}
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void ux500_dma_controller_destroy(struct dma_controller *c)
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{
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struct ux500_dma_controller *controller = container_of(c,
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struct ux500_dma_controller, controller);
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ux500_dma_controller_stop(controller);
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kfree(controller);
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}
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EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy);
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struct dma_controller *
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ux500_dma_controller_create(struct musb *musb, void __iomem *base)
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{
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struct ux500_dma_controller *controller;
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struct platform_device *pdev = to_platform_device(musb->controller);
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struct resource *iomem;
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int ret;
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controller = kzalloc(sizeof(*controller), GFP_KERNEL);
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if (!controller)
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goto kzalloc_fail;
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controller->private_data = musb;
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/* Save physical address for DMA controller. */
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iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iomem) {
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dev_err(musb->controller, "no memory resource defined\n");
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goto plat_get_fail;
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}
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controller->phy_base = (dma_addr_t) iomem->start;
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controller->controller.channel_alloc = ux500_dma_channel_allocate;
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controller->controller.channel_release = ux500_dma_channel_release;
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controller->controller.channel_program = ux500_dma_channel_program;
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controller->controller.channel_abort = ux500_dma_channel_abort;
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controller->controller.is_compatible = ux500_dma_is_compatible;
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ret = ux500_dma_controller_start(controller);
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if (ret)
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goto plat_get_fail;
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return &controller->controller;
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plat_get_fail:
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kfree(controller);
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kzalloc_fail:
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return NULL;
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}
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EXPORT_SYMBOL_GPL(ux500_dma_controller_create);
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