![Ralf Baechle](/assets/img/avatar_default.png)
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
145 lines
4.1 KiB
C
145 lines
4.1 KiB
C
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/**
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*
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* Helper utilities for qlm_jtag.
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*
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*/
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-helper-jtag.h>
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/**
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* Initialize the internal QLM JTAG logic to allow programming
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* of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
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* These functions should only be used at the direction of Cavium
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* Networks. Programming incorrect values into the JTAG chain
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* can cause chip damage.
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*/
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void cvmx_helper_qlm_jtag_init(void)
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{
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union cvmx_ciu_qlm_jtgc jtgc;
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uint32_t clock_div = 0;
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uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
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divisor = (divisor - 1) >> 2;
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/* Convert the divisor into a power of 2 shift */
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while (divisor) {
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clock_div++;
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divisor = divisor >> 1;
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}
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/*
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* Clock divider for QLM JTAG operations. eclk is divided by
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* 2^(CLK_DIV + 2)
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*/
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jtgc.u64 = 0;
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jtgc.s.clk_div = clock_div;
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jtgc.s.mux_sel = 0;
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if (OCTEON_IS_MODEL(OCTEON_CN52XX))
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jtgc.s.bypass = 0x3;
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else
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jtgc.s.bypass = 0xf;
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cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
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cvmx_read_csr(CVMX_CIU_QLM_JTGC);
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}
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/**
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* Write up to 32bits into the QLM jtag chain. Bits are shifted
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* into the MSB and out the LSB, so you should shift in the low
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* order bits followed by the high order bits. The JTAG chain is
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* 4 * 268 bits long, or 1072.
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*
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* @qlm: QLM to shift value into
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* @bits: Number of bits to shift in (1-32).
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* @data: Data to shift in. Bit 0 enters the chain first, followed by
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* bit 1, etc.
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*
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* Returns The low order bits of the JTAG chain that shifted out of the
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* circle.
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*/
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uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
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{
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union cvmx_ciu_qlm_jtgd jtgd;
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jtgd.u64 = 0;
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jtgd.s.shift = 1;
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jtgd.s.shft_cnt = bits - 1;
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jtgd.s.shft_reg = data;
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if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
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jtgd.s.select = 1 << qlm;
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cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
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do {
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jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
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} while (jtgd.s.shift);
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return jtgd.s.shft_reg >> (32 - bits);
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}
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/**
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* Shift long sequences of zeros into the QLM JTAG chain. It is
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* common to need to shift more than 32 bits of zeros into the
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* chain. This function is a convience wrapper around
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* cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
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* zeros at a time.
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*
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* @qlm: QLM to shift zeros into
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* @bits:
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*/
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void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
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{
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while (bits > 0) {
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int n = bits;
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if (n > 32)
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n = 32;
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cvmx_helper_qlm_jtag_shift(qlm, n, 0);
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bits -= n;
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}
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}
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/**
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* Program the QLM JTAG chain into all lanes of the QLM. You must
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* have already shifted in 268*4, or 1072 bits into the JTAG
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* chain. Updating invalid values can possibly cause chip damage.
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*
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* @qlm: QLM to program
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*/
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void cvmx_helper_qlm_jtag_update(int qlm)
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{
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union cvmx_ciu_qlm_jtgd jtgd;
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/* Update the new data */
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jtgd.u64 = 0;
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jtgd.s.update = 1;
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if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
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jtgd.s.select = 1 << qlm;
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cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
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do {
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jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
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} while (jtgd.s.update);
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}
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