296 lines
9.7 KiB
C
296 lines
9.7 KiB
C
/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "core_types.h"
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#include "clk_mgr_internal.h"
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#include "dce/dce_11_0_d.h"
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#include "dce/dce_11_0_sh_mask.h"
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#include "dce110_clk_mgr.h"
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#include "../clk_mgr/dce100/dce_clk_mgr.h"
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/* set register offset */
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#define SR(reg_name)\
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.reg_name = mm ## reg_name
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/* set register offset with instance */
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#define SRI(reg_name, block, id)\
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.reg_name = mm ## block ## id ## _ ## reg_name
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static const struct clk_mgr_registers disp_clk_regs = {
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CLK_COMMON_REG_LIST_DCE_BASE()
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};
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static const struct clk_mgr_shift disp_clk_shift = {
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CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
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};
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static const struct clk_mgr_mask disp_clk_mask = {
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CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
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};
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static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
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/*ClocksStateInvalid - should not be used*/
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{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
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/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
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{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
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/*ClocksStateLow*/
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{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
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/*ClocksStateNominal*/
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{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
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/*ClocksStatePerformance*/
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{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
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static int determine_sclk_from_bounding_box(
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const struct dc *dc,
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int required_sclk)
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{
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int i;
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/*
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* Some asics do not give us sclk levels, so we just report the actual
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* required sclk
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*/
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if (dc->sclk_lvls.num_levels == 0)
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return required_sclk;
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for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
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if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
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return dc->sclk_lvls.clocks_in_khz[i];
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}
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/*
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* even maximum level could not satisfy requirement, this
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* is unexpected at this stage, should have been caught at
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* validation time
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*/
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ASSERT(0);
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return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
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}
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uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
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{
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uint8_t j;
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uint32_t min_vertical_blank_time = -1;
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for (j = 0; j < context->stream_count; j++) {
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struct dc_stream_state *stream = context->streams[j];
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uint32_t vertical_blank_in_pixels = 0;
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uint32_t vertical_blank_time = 0;
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uint32_t vertical_total_min = stream->timing.v_total;
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struct dc_crtc_timing_adjust adjust = stream->adjust;
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if (adjust.v_total_max != adjust.v_total_min)
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vertical_total_min = adjust.v_total_min;
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vertical_blank_in_pixels = stream->timing.h_total *
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(vertical_total_min
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- stream->timing.v_addressable);
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vertical_blank_time = vertical_blank_in_pixels
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* 10000 / stream->timing.pix_clk_100hz;
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if (min_vertical_blank_time > vertical_blank_time)
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min_vertical_blank_time = vertical_blank_time;
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}
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return min_vertical_blank_time;
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}
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void dce110_fill_display_configs(
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const struct dc_state *context,
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struct dm_pp_display_configuration *pp_display_cfg)
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{
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int j;
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int num_cfgs = 0;
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for (j = 0; j < context->stream_count; j++) {
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int k;
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const struct dc_stream_state *stream = context->streams[j];
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struct dm_pp_single_disp_config *cfg =
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&pp_display_cfg->disp_configs[num_cfgs];
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const struct pipe_ctx *pipe_ctx = NULL;
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for (k = 0; k < MAX_PIPES; k++)
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if (stream == context->res_ctx.pipe_ctx[k].stream) {
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pipe_ctx = &context->res_ctx.pipe_ctx[k];
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break;
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}
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ASSERT(pipe_ctx != NULL);
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/* only notify active stream */
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if (stream->dpms_off)
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continue;
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num_cfgs++;
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cfg->signal = pipe_ctx->stream->signal;
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cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
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cfg->src_height = stream->src.height;
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cfg->src_width = stream->src.width;
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cfg->ddi_channel_mapping =
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stream->link->ddi_channel_mapping.raw;
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cfg->transmitter =
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stream->link->link_enc->transmitter;
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cfg->link_settings.lane_count =
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stream->link->cur_link_settings.lane_count;
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cfg->link_settings.link_rate =
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stream->link->cur_link_settings.link_rate;
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cfg->link_settings.link_spread =
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stream->link->cur_link_settings.link_spread;
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cfg->sym_clock = stream->phy_pix_clk;
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/* Round v_refresh*/
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cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
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cfg->v_refresh /= stream->timing.h_total;
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cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
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/ stream->timing.v_total;
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}
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pp_display_cfg->display_count = num_cfgs;
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}
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void dce11_pplib_apply_display_requirements(
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struct dc *dc,
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struct dc_state *context)
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{
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struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
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int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
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if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
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memory_type_multiplier = MEMORY_TYPE_HBM;
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pp_display_cfg->all_displays_in_sync =
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context->bw_ctx.bw.dce.all_displays_in_sync;
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pp_display_cfg->nb_pstate_switch_disable =
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context->bw_ctx.bw.dce.nbp_state_change_enable == false;
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pp_display_cfg->cpu_cc6_disable =
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context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
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pp_display_cfg->cpu_pstate_disable =
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context->bw_ctx.bw.dce.cpup_state_change_enable == false;
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pp_display_cfg->cpu_pstate_separation_time =
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context->bw_ctx.bw.dce.blackout_recovery_time_us;
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/*
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* TODO: determine whether the bandwidth has reached memory's limitation
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* , then change minimum memory clock based on real-time bandwidth
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* limitation.
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*/
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if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
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pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,
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(uint32_t) div64_s64(
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div64_s64(dc->bw_vbios->high_yclk.value,
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memory_type_multiplier), 10000));
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} else {
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pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
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/ memory_type_multiplier;
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}
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pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
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dc,
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context->bw_ctx.bw.dce.sclk_khz);
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/*
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* As workaround for >4x4K lightup set dcfclock to min_engine_clock value.
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* This is not required for less than 5 displays,
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* thus don't request decfclk in dc to avoid impact
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* on power saving.
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*
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*/
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pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?
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pp_display_cfg->min_engine_clock_khz : 0;
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pp_display_cfg->min_engine_clock_deep_sleep_khz
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= context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
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pp_display_cfg->avail_mclk_switch_time_us =
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dce110_get_min_vblank_time_us(context);
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/* TODO: dce11.2*/
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pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
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pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
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dce110_fill_display_configs(context, pp_display_cfg);
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/* TODO: is this still applicable?*/
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if (pp_display_cfg->display_count == 1) {
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const struct dc_crtc_timing *timing =
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&context->streams[0]->timing;
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pp_display_cfg->crtc_index =
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pp_display_cfg->disp_configs[0].pipe_idx;
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pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
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}
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if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
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dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
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}
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static void dce11_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dm_pp_power_level_change_request level_change_req;
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int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
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/*TODO: W/A for dal3 linux, investigate why this works */
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if (!clk_mgr_dce->dfs_bypass_active)
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patched_disp_clk = patched_disp_clk * 115 / 100;
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level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
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/* get max clock state from PPLIB */
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if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
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|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
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if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
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clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
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}
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if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
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context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk);
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clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
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}
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dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
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}
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static struct clk_mgr_funcs dce110_funcs = {
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.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
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.update_clocks = dce11_update_clocks
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};
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void dce110_clk_mgr_construct(
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struct dc_context *ctx,
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struct clk_mgr_internal *clk_mgr)
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{
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dce_clk_mgr_construct(ctx, clk_mgr);
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memcpy(clk_mgr->max_clks_by_state,
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dce110_max_clks_by_state,
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sizeof(dce110_max_clks_by_state));
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clk_mgr->regs = &disp_clk_regs;
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clk_mgr->clk_mgr_shift = &disp_clk_shift;
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clk_mgr->clk_mgr_mask = &disp_clk_mask;
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clk_mgr->base.funcs = &dce110_funcs;
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}
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