![Uwe Kleine-König](/assets/img/avatar_default.png)
The driver recently learned to handle platform ids. Make use of this new feature. The up side is that the driver needs less knowledge about the spi interfaces used on different SoCs. Acked-by: Jason Wang <jason77.wang@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
637 lines
14 KiB
C
637 lines
14 KiB
C
/*
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* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/math64.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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#include <mach/clock.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
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/* CCM register addresses */
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#define CCM_CSCR IO_ADDR_CCM(0x0)
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#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
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#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
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#define CCM_PCDR IO_ADDR_CCM(0x20)
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#define CCM_CSCR_CLKO_OFFSET 29
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#define CCM_CSCR_CLKO_MASK (0x7 << 29)
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#define CCM_CSCR_USB_OFFSET 26
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#define CCM_CSCR_USB_MASK (0x7 << 26)
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#define CCM_CSCR_OSC_EN_SHIFT 17
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#define CCM_CSCR_SYSTEM_SEL (1 << 16)
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#define CCM_CSCR_BCLK_OFFSET 10
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#define CCM_CSCR_BCLK_MASK (0xf << 10)
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#define CCM_CSCR_PRESC (1 << 15)
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#define CCM_PCDR_PCLK3_OFFSET 16
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#define CCM_PCDR_PCLK3_MASK (0x7f << 16)
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#define CCM_PCDR_PCLK2_OFFSET 4
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#define CCM_PCDR_PCLK2_MASK (0xf << 4)
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#define CCM_PCDR_PCLK1_OFFSET 0
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#define CCM_PCDR_PCLK1_MASK 0xf
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#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
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/* SCM register addresses */
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#define SCM_GCCR IO_ADDR_SCM(0xc)
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#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
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#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
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#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
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#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
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static int _clk_enable(struct clk *clk)
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{
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unsigned int reg;
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reg = __raw_readl(clk->enable_reg);
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reg |= 1 << clk->enable_shift;
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__raw_writel(reg, clk->enable_reg);
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return 0;
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}
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static void _clk_disable(struct clk *clk)
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{
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unsigned int reg;
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(1 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
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struct clk *parent)
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{
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int i;
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for (i = 0; i < size; i++)
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if (parent == clk_arr[i])
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return i;
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return -EINVAL;
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}
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static unsigned long
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_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
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{
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int div;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (parent_rate % rate)
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div++;
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if (div > limit)
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div = limit;
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return parent_rate / div;
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}
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static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk->parent->round_rate(clk->parent, rate);
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}
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static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
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{
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return clk->parent->set_rate(clk->parent, rate);
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}
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static unsigned long clk16m_get_rate(struct clk *clk)
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{
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return 16000000;
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}
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static struct clk clk16m = {
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.get_rate = clk16m_get_rate,
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.enable = _clk_enable,
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.enable_reg = CCM_CSCR,
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.enable_shift = CCM_CSCR_OSC_EN_SHIFT,
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.disable = _clk_disable,
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};
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/* in Hz */
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static unsigned long clk32_rate;
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static unsigned long clk32_get_rate(struct clk *clk)
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{
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return clk32_rate;
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}
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static struct clk clk32 = {
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.get_rate = clk32_get_rate,
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};
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static unsigned long clk32_premult_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) * 512;
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}
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static struct clk clk32_premult = {
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.parent = &clk32,
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.get_rate = clk32_premult_get_rate,
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};
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static const struct clk *prem_clk_clocks[] = {
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&clk32_premult,
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&clk16m,
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};
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static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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int i;
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unsigned int reg = __raw_readl(CCM_CSCR);
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i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
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parent);
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switch (i) {
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case 0:
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reg &= ~CCM_CSCR_SYSTEM_SEL;
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break;
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case 1:
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reg |= CCM_CSCR_SYSTEM_SEL;
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break;
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default:
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return i;
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}
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__raw_writel(reg, CCM_CSCR);
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return 0;
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}
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static struct clk prem_clk = {
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.set_parent = prem_clk_set_parent,
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};
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static unsigned long system_clk_get_rate(struct clk *clk)
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{
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return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
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clk_get_rate(clk->parent));
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}
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static struct clk system_clk = {
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.parent = &prem_clk,
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.get_rate = system_clk_get_rate,
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};
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static unsigned long mcu_clk_get_rate(struct clk *clk)
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{
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return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
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clk_get_rate(clk->parent));
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}
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static struct clk mcu_clk = {
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.parent = &clk32_premult,
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.get_rate = mcu_clk_get_rate,
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};
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static unsigned long fclk_get_rate(struct clk *clk)
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{
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unsigned long fclk = clk_get_rate(clk->parent);
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if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
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fclk /= 2;
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return fclk;
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}
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static struct clk fclk = {
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.parent = &mcu_clk,
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.get_rate = fclk_get_rate,
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};
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/*
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* get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
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*/
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static unsigned long hclk_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
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CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
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}
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static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 16);
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}
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static int hclk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 16 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_CSCR);
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reg &= ~CCM_CSCR_BCLK_MASK;
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reg |= div << CCM_CSCR_BCLK_OFFSET;
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__raw_writel(reg, CCM_CSCR);
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return 0;
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}
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static struct clk hclk = {
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.parent = &system_clk,
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.get_rate = hclk_get_rate,
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.round_rate = hclk_round_rate,
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.set_rate = hclk_set_rate,
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};
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static unsigned long clk48m_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
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CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
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}
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static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 8);
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}
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static int clk48m_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 8 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_CSCR);
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reg &= ~CCM_CSCR_USB_MASK;
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reg |= div << CCM_CSCR_USB_OFFSET;
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__raw_writel(reg, CCM_CSCR);
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return 0;
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}
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static struct clk clk48m = {
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.parent = &system_clk,
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.get_rate = clk48m_get_rate,
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.round_rate = clk48m_round_rate,
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.set_rate = clk48m_set_rate,
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};
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/*
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* get peripheral clock 1 ( UART[12], Timer[12], PWM )
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*/
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static unsigned long perclk1_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
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CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
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}
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static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 16);
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}
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static int perclk1_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 16 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_PCDR);
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reg &= ~CCM_PCDR_PCLK1_MASK;
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reg |= div << CCM_PCDR_PCLK1_OFFSET;
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__raw_writel(reg, CCM_PCDR);
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return 0;
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}
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/*
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* get peripheral clock 2 ( LCD, SD, SPI[12] )
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*/
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static unsigned long perclk2_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
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CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
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}
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static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 16);
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}
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static int perclk2_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 16 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_PCDR);
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reg &= ~CCM_PCDR_PCLK2_MASK;
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reg |= div << CCM_PCDR_PCLK2_OFFSET;
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__raw_writel(reg, CCM_PCDR);
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return 0;
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}
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/*
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* get peripheral clock 3 ( SSI )
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*/
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static unsigned long perclk3_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
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CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
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}
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static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 128);
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}
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static int perclk3_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 128 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_PCDR);
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reg &= ~CCM_PCDR_PCLK3_MASK;
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reg |= div << CCM_PCDR_PCLK3_OFFSET;
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__raw_writel(reg, CCM_PCDR);
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return 0;
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}
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static struct clk perclk[] = {
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{
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.id = 0,
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.parent = &system_clk,
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.get_rate = perclk1_get_rate,
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.round_rate = perclk1_round_rate,
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.set_rate = perclk1_set_rate,
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}, {
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.id = 1,
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.parent = &system_clk,
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.get_rate = perclk2_get_rate,
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.round_rate = perclk2_round_rate,
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.set_rate = perclk2_set_rate,
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}, {
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.id = 2,
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.parent = &system_clk,
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.get_rate = perclk3_get_rate,
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.round_rate = perclk3_round_rate,
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.set_rate = perclk3_set_rate,
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}
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};
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static const struct clk *clko_clocks[] = {
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&perclk[0],
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&hclk,
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&clk48m,
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&clk16m,
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&prem_clk,
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&fclk,
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};
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static int clko_set_parent(struct clk *clk, struct clk *parent)
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{
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int i;
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unsigned int reg;
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i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
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if (i < 0)
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return i;
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reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
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reg |= i << CCM_CSCR_CLKO_OFFSET;
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__raw_writel(reg, CCM_CSCR);
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if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
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clk->set_rate = _clk_parent_set_rate;
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clk->round_rate = _clk_parent_round_rate;
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} else {
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clk->set_rate = NULL;
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clk->round_rate = NULL;
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}
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return 0;
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}
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static struct clk clko_clk = {
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.set_parent = clko_set_parent,
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};
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static struct clk dma_clk = {
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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.enable = _clk_enable,
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.enable_reg = SCM_GCCR,
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.enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
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.disable = _clk_disable,
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};
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static struct clk csi_clk = {
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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.enable = _clk_enable,
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.enable_reg = SCM_GCCR,
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.enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
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.disable = _clk_disable,
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};
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static struct clk mma_clk = {
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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.enable = _clk_enable,
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.enable_reg = SCM_GCCR,
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.enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
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.disable = _clk_disable,
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};
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static struct clk usbd_clk = {
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.parent = &clk48m,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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.enable = _clk_enable,
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.enable_reg = SCM_GCCR,
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.enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
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.disable = _clk_disable,
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};
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static struct clk gpt_clk = {
|
|
.parent = &perclk[0],
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk uart_clk = {
|
|
.parent = &perclk[0],
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk i2c_clk = {
|
|
.parent = &hclk,
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk spi_clk = {
|
|
.parent = &perclk[1],
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk sdhc_clk = {
|
|
.parent = &perclk[1],
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk lcdc_clk = {
|
|
.parent = &perclk[1],
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk mshc_clk = {
|
|
.parent = &hclk,
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk ssi_clk = {
|
|
.parent = &perclk[2],
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk rtc_clk = {
|
|
.parent = &clk32,
|
|
};
|
|
|
|
#define _REGISTER_CLOCK(d, n, c) \
|
|
{ \
|
|
.dev_id = d, \
|
|
.con_id = n, \
|
|
.clk = &c, \
|
|
},
|
|
static struct clk_lookup lookups[] __initdata = {
|
|
_REGISTER_CLOCK(NULL, "dma", dma_clk)
|
|
_REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
|
|
_REGISTER_CLOCK(NULL, "mma", mma_clk)
|
|
_REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
|
|
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
|
|
_REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
|
|
_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
|
|
_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
|
|
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
|
|
_REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
|
|
_REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
|
|
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
|
|
_REGISTER_CLOCK(NULL, "mshc", mshc_clk)
|
|
_REGISTER_CLOCK(NULL, "ssi", ssi_clk)
|
|
_REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
|
|
};
|
|
|
|
int __init mx1_clocks_init(unsigned long fref)
|
|
{
|
|
unsigned int reg;
|
|
|
|
/* disable clocks we are able to */
|
|
__raw_writel(0, SCM_GCCR);
|
|
|
|
clk32_rate = fref;
|
|
reg = __raw_readl(CCM_CSCR);
|
|
|
|
/* detect clock reference for system PLL */
|
|
if (reg & CCM_CSCR_SYSTEM_SEL) {
|
|
prem_clk.parent = &clk16m;
|
|
} else {
|
|
/* ensure that oscillator is disabled */
|
|
reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
|
|
__raw_writel(reg, CCM_CSCR);
|
|
prem_clk.parent = &clk32_premult;
|
|
}
|
|
|
|
/* detect reference for CLKO */
|
|
reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
|
|
clko_clk.parent = (struct clk *)clko_clocks[reg];
|
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
|
|
|
clk_enable(&hclk);
|
|
clk_enable(&fclk);
|
|
|
|
mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
|
|
MX1_TIM1_INT);
|
|
|
|
return 0;
|
|
}
|