![Colin Cross](/assets/img/avatar_default.png)
- Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by: Colin Cross <ccross@android.com>
174 lines
3.7 KiB
C
174 lines
3.7 KiB
C
/*
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* arch/arm/mach-tegra/include/mach/clock.h
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_CLOCK_H
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#define __MACH_TEGRA_CLOCK_H
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#include <linux/list.h>
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#include <asm/clkdev.h>
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#define DIV_BUS (1 << 0)
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#define DIV_U71 (1 << 1)
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#define DIV_U71_FIXED (1 << 2)
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#define DIV_2 (1 << 3)
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#define DIV_U16 (1 << 4)
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#define PLL_FIXED (1 << 5)
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#define PLL_HAS_CPCON (1 << 6)
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#define MUX (1 << 7)
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#define PLLD (1 << 8)
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#define PERIPH_NO_RESET (1 << 9)
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#define PERIPH_NO_ENB (1 << 10)
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#define PERIPH_EMC_ENB (1 << 11)
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#define PERIPH_MANUAL_RESET (1 << 12)
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#define PLL_ALT_MISC_REG (1 << 13)
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#define PLLU (1 << 14)
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#define ENABLE_ON_INIT (1 << 28)
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struct clk;
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struct regulator;
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struct dvfs_table {
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unsigned long rate;
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int millivolts;
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};
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struct dvfs_process_id_table {
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int process_id;
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struct dvfs_table *table;
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};
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struct dvfs {
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struct regulator *reg;
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struct dvfs_table *table;
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int max_millivolts;
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int process_id_table_length;
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const char *reg_id;
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bool cpu;
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struct dvfs_process_id_table process_id_table[];
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};
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struct clk_mux_sel {
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struct clk *input;
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u32 value;
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};
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struct clk_pll_table {
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unsigned long input_rate;
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unsigned long output_rate;
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u16 n;
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u16 m;
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u8 p;
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u8 cpcon;
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};
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struct clk_ops {
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void (*init)(struct clk *);
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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int (*set_parent)(struct clk *, struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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};
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enum clk_state {
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UNINITIALIZED = 0,
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ON,
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OFF,
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};
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struct clk {
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/* node for master clocks list */
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struct list_head node;
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struct list_head children; /* list of children */
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struct list_head sibling; /* node for children */
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dent;
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struct dentry *parent_dent;
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#endif
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struct clk_ops *ops;
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struct clk *parent;
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struct clk_lookup lookup;
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unsigned long rate;
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unsigned long max_rate;
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u32 flags;
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u32 refcnt;
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const char *name;
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u32 reg;
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u32 reg_shift;
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unsigned int clk_num;
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enum clk_state state;
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#ifdef CONFIG_DEBUG_FS
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bool set;
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#endif
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/* PLL */
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unsigned long input_min;
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unsigned long input_max;
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unsigned long cf_min;
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unsigned long cf_max;
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unsigned long vco_min;
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unsigned long vco_max;
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const struct clk_pll_table *pll_table;
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/* DIV */
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u32 div;
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u32 mul;
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/* MUX */
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const struct clk_mux_sel *inputs;
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u32 sel;
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u32 reg_mask;
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/* Virtual cpu clock */
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struct clk *main;
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struct clk *backup;
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struct dvfs *dvfs;
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};
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struct clk_duplicate {
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const char *name;
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struct clk_lookup lookup;
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};
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struct tegra_clk_init_table {
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const char *name;
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const char *parent;
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unsigned long rate;
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bool enabled;
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};
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void tegra2_init_clocks(void);
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void tegra2_periph_reset_deassert(struct clk *c);
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void tegra2_periph_reset_assert(struct clk *c);
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void clk_init(struct clk *clk);
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struct clk *tegra_get_clock_by_name(const char *name);
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unsigned long clk_measure_input_freq(void);
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void clk_disable_locked(struct clk *c);
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int clk_enable_locked(struct clk *c);
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int clk_set_parent_locked(struct clk *c, struct clk *parent);
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int clk_set_rate_locked(struct clk *c, unsigned long rate);
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int clk_reparent(struct clk *c, struct clk *parent);
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void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
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#endif
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