![Arun Kumar K](/assets/img/avatar_default.png)
Adds the google peach-pit board dts file which uses exynos5420 SoC. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
148 lines
2.9 KiB
Plaintext
148 lines
2.9 KiB
Plaintext
/*
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* Google Peach Pit Rev 6+ board device tree source
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*
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* Copyright (c) 2014 Google, Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "exynos5420.dtsi"
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/ {
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model = "Google Peach Pit Rev 6+";
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compatible = "google,pit-rev16",
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"google,pit-rev15", "google,pit-rev14",
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"google,pit-rev13", "google,pit-rev12",
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"google,pit-rev11", "google,pit-rev10",
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"google,pit-rev9", "google,pit-rev8",
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"google,pit-rev7", "google,pit-rev6",
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"google,pit", "google,peach","samsung,exynos5420",
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"samsung,exynos5";
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memory {
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reg = <0x20000000 0x80000000>;
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};
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fixed-rate-clocks {
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oscclk {
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compatible = "samsung,exynos5420-oscclk";
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clock-frequency = <24000000>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&power_key_irq>;
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power {
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label = "Power";
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gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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gpio-key,wakeup;
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};
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm 0 1000000 0>;
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brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
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default-brightness-level = <7>;
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pinctrl-0 = <&pwm0_out>;
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pinctrl-names = "default";
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};
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};
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&pinctrl_0 {
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tpm_irq: tpm-irq {
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samsung,pins = "gpx1-0";
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samsung,pin-function = <0>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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power_key_irq: power-key-irq {
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samsung,pins = "gpx1-2";
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samsung,pin-function = <0>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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};
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&rtc {
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status = "okay";
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};
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&uart_3 {
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status = "okay";
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};
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&mmc_0 {
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status = "okay";
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num-slots = <1>;
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broken-cd;
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caps2-mmc-hs200-1_8v;
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supports-highspeed;
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non-removable;
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card-detect-delay = <200>;
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clock-frequency = <400000000>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <0 4>;
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samsung,dw-mshc-ddr-timing = <0 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
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slot@0 {
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reg = <0>;
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bus-width = <8>;
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};
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};
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&mmc_2 {
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status = "okay";
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num-slots = <1>;
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supports-highspeed;
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card-detect-delay = <200>;
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clock-frequency = <400000000>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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};
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};
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&hsi2c_9 {
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status = "okay";
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clock-frequency = <400000>;
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tpm@20 {
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compatible = "infineon,slb9645tt";
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reg = <0x20>;
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/* Unused irq; but still need to configure the pins */
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pinctrl-names = "default";
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pinctrl-0 = <&tpm_irq>;
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};
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};
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/*
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* Use longest HW watchdog in SoC (32 seconds) since the hardware
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* watchdog provides no debugging information (compared to soft/hard
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* lockup detectors) and so should be last resort.
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*/
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&watchdog {
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timeout-sec = <32>;
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};
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