![Peter Rosin](/assets/img/avatar_default.png)
With the help from drm_atomic_helper_check_plane_state function, clipping now handles planes to be partially or totally off-screen. The plane is disabled if it is not visible. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190110151020.30468-4-peda@axentia.se
1024 lines
26 KiB
C
1024 lines
26 KiB
C
/*
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* Copyright (C) 2014 Free Electrons
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* Copyright (C) 2014 Atmel
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "atmel_hlcdc_dc.h"
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/**
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* Atmel HLCDC Plane state structure.
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*
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* @base: DRM plane state
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* @crtc_x: x position of the plane relative to the CRTC
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* @crtc_y: y position of the plane relative to the CRTC
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* @crtc_w: visible width of the plane
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* @crtc_h: visible height of the plane
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* @src_x: x buffer position
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* @src_y: y buffer position
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* @src_w: buffer width
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* @src_h: buffer height
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* @disc_x: x discard position
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* @disc_y: y discard position
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* @disc_w: discard width
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* @disc_h: discard height
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* @bpp: bytes per pixel deduced from pixel_format
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* @offsets: offsets to apply to the GEM buffers
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* @xstride: value to add to the pixel pointer between each line
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* @pstride: value to add to the pixel pointer between each pixel
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* @nplanes: number of planes (deduced from pixel_format)
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* @dscrs: DMA descriptors
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*/
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struct atmel_hlcdc_plane_state {
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struct drm_plane_state base;
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int crtc_x;
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int crtc_y;
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unsigned int crtc_w;
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unsigned int crtc_h;
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uint32_t src_x;
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uint32_t src_y;
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uint32_t src_w;
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uint32_t src_h;
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int disc_x;
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int disc_y;
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int disc_w;
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int disc_h;
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int ahb_id;
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/* These fields are private and should not be touched */
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int bpp[ATMEL_HLCDC_LAYER_MAX_PLANES];
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unsigned int offsets[ATMEL_HLCDC_LAYER_MAX_PLANES];
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int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
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int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
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int nplanes;
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/* DMA descriptors. */
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struct atmel_hlcdc_dma_channel_dscr *dscrs[ATMEL_HLCDC_LAYER_MAX_PLANES];
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};
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static inline struct atmel_hlcdc_plane_state *
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drm_plane_state_to_atmel_hlcdc_plane_state(struct drm_plane_state *s)
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{
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return container_of(s, struct atmel_hlcdc_plane_state, base);
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}
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#define SUBPIXEL_MASK 0xffff
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static uint32_t rgb_formats[] = {
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DRM_FORMAT_C8,
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DRM_FORMAT_XRGB4444,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_RGBA4444,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_RGBA8888,
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};
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struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats = {
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.formats = rgb_formats,
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.nformats = ARRAY_SIZE(rgb_formats),
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};
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static uint32_t rgb_and_yuv_formats[] = {
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DRM_FORMAT_C8,
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DRM_FORMAT_XRGB4444,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_RGBA4444,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_RGBA8888,
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DRM_FORMAT_AYUV,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_UYVY,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_NV21,
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DRM_FORMAT_NV61,
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DRM_FORMAT_YUV422,
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DRM_FORMAT_YUV420,
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};
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struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats = {
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.formats = rgb_and_yuv_formats,
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.nformats = ARRAY_SIZE(rgb_and_yuv_formats),
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};
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static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode)
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{
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switch (format) {
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case DRM_FORMAT_C8:
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*mode = ATMEL_HLCDC_C8_MODE;
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break;
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case DRM_FORMAT_XRGB4444:
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*mode = ATMEL_HLCDC_XRGB4444_MODE;
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break;
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case DRM_FORMAT_ARGB4444:
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*mode = ATMEL_HLCDC_ARGB4444_MODE;
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break;
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case DRM_FORMAT_RGBA4444:
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*mode = ATMEL_HLCDC_RGBA4444_MODE;
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break;
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case DRM_FORMAT_RGB565:
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*mode = ATMEL_HLCDC_RGB565_MODE;
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break;
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case DRM_FORMAT_RGB888:
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*mode = ATMEL_HLCDC_RGB888_MODE;
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break;
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case DRM_FORMAT_ARGB1555:
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*mode = ATMEL_HLCDC_ARGB1555_MODE;
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break;
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case DRM_FORMAT_XRGB8888:
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*mode = ATMEL_HLCDC_XRGB8888_MODE;
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break;
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case DRM_FORMAT_ARGB8888:
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*mode = ATMEL_HLCDC_ARGB8888_MODE;
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break;
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case DRM_FORMAT_RGBA8888:
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*mode = ATMEL_HLCDC_RGBA8888_MODE;
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break;
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case DRM_FORMAT_AYUV:
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*mode = ATMEL_HLCDC_AYUV_MODE;
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break;
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case DRM_FORMAT_YUYV:
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*mode = ATMEL_HLCDC_YUYV_MODE;
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break;
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case DRM_FORMAT_UYVY:
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*mode = ATMEL_HLCDC_UYVY_MODE;
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break;
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case DRM_FORMAT_YVYU:
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*mode = ATMEL_HLCDC_YVYU_MODE;
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break;
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case DRM_FORMAT_VYUY:
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*mode = ATMEL_HLCDC_VYUY_MODE;
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break;
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case DRM_FORMAT_NV21:
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*mode = ATMEL_HLCDC_NV21_MODE;
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break;
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case DRM_FORMAT_NV61:
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*mode = ATMEL_HLCDC_NV61_MODE;
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break;
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case DRM_FORMAT_YUV420:
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*mode = ATMEL_HLCDC_YUV420_MODE;
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break;
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case DRM_FORMAT_YUV422:
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*mode = ATMEL_HLCDC_YUV422_MODE;
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static u32 heo_downscaling_xcoef[] = {
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0x11343311,
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0x000000f7,
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0x1635300c,
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0x000000f9,
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0x1b362c08,
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0x000000fb,
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0x1f372804,
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0x000000fe,
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0x24382400,
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0x00000000,
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0x28371ffe,
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0x00000004,
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0x2c361bfb,
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0x00000008,
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0x303516f9,
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0x0000000c,
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};
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static u32 heo_downscaling_ycoef[] = {
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0x00123737,
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0x00173732,
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0x001b382d,
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0x001f3928,
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0x00243824,
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0x0028391f,
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0x002d381b,
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0x00323717,
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};
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static u32 heo_upscaling_xcoef[] = {
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0xf74949f7,
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0x00000000,
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0xf55f33fb,
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0x000000fe,
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0xf5701efe,
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0x000000ff,
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0xf87c0dff,
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0x00000000,
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0x00800000,
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0x00000000,
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0x0d7cf800,
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0x000000ff,
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0x1e70f5ff,
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0x000000fe,
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0x335ff5fe,
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0x000000fb,
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};
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static u32 heo_upscaling_ycoef[] = {
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0x00004040,
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0x00075920,
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0x00056f0c,
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0x00027b03,
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0x00008000,
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0x00037b02,
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0x000c6f05,
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0x00205907,
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};
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#define ATMEL_HLCDC_XPHIDEF 4
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#define ATMEL_HLCDC_YPHIDEF 4
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static u32 atmel_hlcdc_plane_phiscaler_get_factor(u32 srcsize,
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u32 dstsize,
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u32 phidef)
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{
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u32 factor, max_memsize;
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factor = (256 * ((8 * (srcsize - 1)) - phidef)) / (dstsize - 1);
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max_memsize = ((factor * (dstsize - 1)) + (256 * phidef)) / 2048;
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if (max_memsize > srcsize - 1)
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factor--;
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return factor;
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}
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static void
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atmel_hlcdc_plane_scaler_set_phicoeff(struct atmel_hlcdc_plane *plane,
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const u32 *coeff_tab, int size,
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unsigned int cfg_offs)
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{
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int i;
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for (i = 0; i < size; i++)
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atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i,
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coeff_tab[i]);
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}
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void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane,
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struct atmel_hlcdc_plane_state *state)
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{
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const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
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u32 xfactor, yfactor;
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if (!desc->layout.scaler_config)
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return;
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if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) {
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atmel_hlcdc_layer_write_cfg(&plane->layer,
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desc->layout.scaler_config, 0);
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return;
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}
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if (desc->layout.phicoeffs.x) {
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xfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_w,
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state->crtc_w,
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ATMEL_HLCDC_XPHIDEF);
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yfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_h,
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state->crtc_h,
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ATMEL_HLCDC_YPHIDEF);
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atmel_hlcdc_plane_scaler_set_phicoeff(plane,
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state->crtc_w < state->src_w ?
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heo_downscaling_xcoef :
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heo_upscaling_xcoef,
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ARRAY_SIZE(heo_upscaling_xcoef),
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desc->layout.phicoeffs.x);
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atmel_hlcdc_plane_scaler_set_phicoeff(plane,
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state->crtc_h < state->src_h ?
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heo_downscaling_ycoef :
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heo_upscaling_ycoef,
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ARRAY_SIZE(heo_upscaling_ycoef),
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desc->layout.phicoeffs.y);
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} else {
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xfactor = (1024 * state->src_w) / state->crtc_w;
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yfactor = (1024 * state->src_h) / state->crtc_h;
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}
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atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config,
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ATMEL_HLCDC_LAYER_SCALER_ENABLE |
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ATMEL_HLCDC_LAYER_SCALER_FACTORS(xfactor,
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yfactor));
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}
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static void
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atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
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struct atmel_hlcdc_plane_state *state)
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{
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const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
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if (desc->layout.size)
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atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size,
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ATMEL_HLCDC_LAYER_SIZE(state->crtc_w,
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state->crtc_h));
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if (desc->layout.memsize)
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atmel_hlcdc_layer_write_cfg(&plane->layer,
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desc->layout.memsize,
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ATMEL_HLCDC_LAYER_SIZE(state->src_w,
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state->src_h));
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if (desc->layout.pos)
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atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.pos,
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ATMEL_HLCDC_LAYER_POS(state->crtc_x,
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state->crtc_y));
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atmel_hlcdc_plane_setup_scaler(plane, state);
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}
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static void
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atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
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struct atmel_hlcdc_plane_state *state)
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{
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unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id;
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const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
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const struct drm_format_info *format = state->base.fb->format;
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/*
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* Rotation optimization is not working on RGB888 (rotation is still
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* working but without any optimization).
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*/
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if (format->format == DRM_FORMAT_RGB888)
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cfg |= ATMEL_HLCDC_LAYER_DMA_ROTDIS;
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atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG,
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cfg);
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cfg = ATMEL_HLCDC_LAYER_DMA;
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if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) {
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cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL |
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ATMEL_HLCDC_LAYER_ITER;
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if (format->has_alpha)
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cfg |= ATMEL_HLCDC_LAYER_LAEN;
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else
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cfg |= ATMEL_HLCDC_LAYER_GAEN |
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ATMEL_HLCDC_LAYER_GA(state->base.alpha >> 8);
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}
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if (state->disc_h && state->disc_w)
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cfg |= ATMEL_HLCDC_LAYER_DISCEN;
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atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config,
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cfg);
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}
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static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,
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struct atmel_hlcdc_plane_state *state)
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{
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u32 cfg;
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int ret;
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ret = atmel_hlcdc_format_to_plane_mode(state->base.fb->format->format,
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&cfg);
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if (ret)
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return;
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if ((state->base.fb->format->format == DRM_FORMAT_YUV422 ||
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state->base.fb->format->format == DRM_FORMAT_NV61) &&
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drm_rotation_90_or_270(state->base.rotation))
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cfg |= ATMEL_HLCDC_YUV422ROT;
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atmel_hlcdc_layer_write_cfg(&plane->layer,
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ATMEL_HLCDC_LAYER_FORMAT_CFG, cfg);
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}
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static void atmel_hlcdc_plane_update_clut(struct atmel_hlcdc_plane *plane,
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struct atmel_hlcdc_plane_state *state)
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{
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struct drm_crtc *crtc = state->base.crtc;
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struct drm_color_lut *lut;
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int idx;
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if (!crtc || !crtc->state)
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return;
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if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
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return;
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lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
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for (idx = 0; idx < ATMEL_HLCDC_CLUT_SIZE; idx++, lut++) {
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u32 val = ((lut->red << 8) & 0xff0000) |
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(lut->green & 0xff00) |
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(lut->blue >> 8);
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atmel_hlcdc_layer_write_clut(&plane->layer, idx, val);
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}
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}
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static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane,
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struct atmel_hlcdc_plane_state *state)
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{
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const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
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struct drm_framebuffer *fb = state->base.fb;
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u32 sr;
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int i;
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sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
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for (i = 0; i < state->nplanes; i++) {
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struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, i);
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state->dscrs[i]->addr = gem->paddr + state->offsets[i];
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atmel_hlcdc_layer_write_reg(&plane->layer,
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ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
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state->dscrs[i]->self);
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if (!(sr & ATMEL_HLCDC_LAYER_EN)) {
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atmel_hlcdc_layer_write_reg(&plane->layer,
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ATMEL_HLCDC_LAYER_PLANE_ADDR(i),
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state->dscrs[i]->addr);
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atmel_hlcdc_layer_write_reg(&plane->layer,
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ATMEL_HLCDC_LAYER_PLANE_CTRL(i),
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state->dscrs[i]->ctrl);
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atmel_hlcdc_layer_write_reg(&plane->layer,
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ATMEL_HLCDC_LAYER_PLANE_NEXT(i),
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state->dscrs[i]->self);
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}
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if (desc->layout.xstride[i])
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atmel_hlcdc_layer_write_cfg(&plane->layer,
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desc->layout.xstride[i],
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state->xstride[i]);
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if (desc->layout.pstride[i])
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atmel_hlcdc_layer_write_cfg(&plane->layer,
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desc->layout.pstride[i],
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state->pstride[i]);
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}
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}
|
|
|
|
int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state)
|
|
{
|
|
unsigned int ahb_load[2] = { };
|
|
struct drm_plane *plane;
|
|
|
|
drm_atomic_crtc_state_for_each_plane(plane, c_state) {
|
|
struct atmel_hlcdc_plane_state *plane_state;
|
|
struct drm_plane_state *plane_s;
|
|
unsigned int pixels, load = 0;
|
|
int i;
|
|
|
|
plane_s = drm_atomic_get_plane_state(c_state->state, plane);
|
|
if (IS_ERR(plane_s))
|
|
return PTR_ERR(plane_s);
|
|
|
|
plane_state =
|
|
drm_plane_state_to_atmel_hlcdc_plane_state(plane_s);
|
|
|
|
pixels = (plane_state->src_w * plane_state->src_h) -
|
|
(plane_state->disc_w * plane_state->disc_h);
|
|
|
|
for (i = 0; i < plane_state->nplanes; i++)
|
|
load += pixels * plane_state->bpp[i];
|
|
|
|
if (ahb_load[0] <= ahb_load[1])
|
|
plane_state->ahb_id = 0;
|
|
else
|
|
plane_state->ahb_id = 1;
|
|
|
|
ahb_load[plane_state->ahb_id] += load;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state)
|
|
{
|
|
int disc_x = 0, disc_y = 0, disc_w = 0, disc_h = 0;
|
|
const struct atmel_hlcdc_layer_cfg_layout *layout;
|
|
struct atmel_hlcdc_plane_state *primary_state;
|
|
struct drm_plane_state *primary_s;
|
|
struct atmel_hlcdc_plane *primary;
|
|
struct drm_plane *ovl;
|
|
|
|
primary = drm_plane_to_atmel_hlcdc_plane(c_state->crtc->primary);
|
|
layout = &primary->layer.desc->layout;
|
|
if (!layout->disc_pos || !layout->disc_size)
|
|
return 0;
|
|
|
|
primary_s = drm_atomic_get_plane_state(c_state->state,
|
|
&primary->base);
|
|
if (IS_ERR(primary_s))
|
|
return PTR_ERR(primary_s);
|
|
|
|
primary_state = drm_plane_state_to_atmel_hlcdc_plane_state(primary_s);
|
|
|
|
drm_atomic_crtc_state_for_each_plane(ovl, c_state) {
|
|
struct atmel_hlcdc_plane_state *ovl_state;
|
|
struct drm_plane_state *ovl_s;
|
|
|
|
if (ovl == c_state->crtc->primary)
|
|
continue;
|
|
|
|
ovl_s = drm_atomic_get_plane_state(c_state->state, ovl);
|
|
if (IS_ERR(ovl_s))
|
|
return PTR_ERR(ovl_s);
|
|
|
|
ovl_state = drm_plane_state_to_atmel_hlcdc_plane_state(ovl_s);
|
|
|
|
if (!ovl_s->visible ||
|
|
!ovl_s->fb ||
|
|
ovl_s->fb->format->has_alpha ||
|
|
ovl_s->alpha != DRM_BLEND_ALPHA_OPAQUE)
|
|
continue;
|
|
|
|
/* TODO: implement a smarter hidden area detection */
|
|
if (ovl_state->crtc_h * ovl_state->crtc_w < disc_h * disc_w)
|
|
continue;
|
|
|
|
disc_x = ovl_state->crtc_x;
|
|
disc_y = ovl_state->crtc_y;
|
|
disc_h = ovl_state->crtc_h;
|
|
disc_w = ovl_state->crtc_w;
|
|
}
|
|
|
|
primary_state->disc_x = disc_x;
|
|
primary_state->disc_y = disc_y;
|
|
primary_state->disc_w = disc_w;
|
|
primary_state->disc_h = disc_h;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
atmel_hlcdc_plane_update_disc_area(struct atmel_hlcdc_plane *plane,
|
|
struct atmel_hlcdc_plane_state *state)
|
|
{
|
|
const struct atmel_hlcdc_layer_cfg_layout *layout;
|
|
|
|
layout = &plane->layer.desc->layout;
|
|
if (!layout->disc_pos || !layout->disc_size)
|
|
return;
|
|
|
|
atmel_hlcdc_layer_write_cfg(&plane->layer, layout->disc_pos,
|
|
ATMEL_HLCDC_LAYER_DISC_POS(state->disc_x,
|
|
state->disc_y));
|
|
|
|
atmel_hlcdc_layer_write_cfg(&plane->layer, layout->disc_size,
|
|
ATMEL_HLCDC_LAYER_DISC_SIZE(state->disc_w,
|
|
state->disc_h));
|
|
}
|
|
|
|
static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p,
|
|
struct drm_plane_state *s)
|
|
{
|
|
struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
|
|
struct atmel_hlcdc_plane_state *state =
|
|
drm_plane_state_to_atmel_hlcdc_plane_state(s);
|
|
const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
|
|
struct drm_framebuffer *fb = state->base.fb;
|
|
const struct drm_display_mode *mode;
|
|
struct drm_crtc_state *crtc_state;
|
|
unsigned int tmp;
|
|
int hsub = 1;
|
|
int vsub = 1;
|
|
int ret;
|
|
int i;
|
|
|
|
if (!state->base.crtc || !fb)
|
|
return 0;
|
|
|
|
crtc_state = drm_atomic_get_existing_crtc_state(s->state, s->crtc);
|
|
mode = &crtc_state->adjusted_mode;
|
|
|
|
ret = drm_atomic_helper_check_plane_state(s, crtc_state,
|
|
(1 << 16) / 2048,
|
|
INT_MAX, true, true);
|
|
if (ret || !s->visible)
|
|
return ret;
|
|
|
|
state->src_x = s->src.x1;
|
|
state->src_y = s->src.y1;
|
|
state->src_w = drm_rect_width(&s->src);
|
|
state->src_h = drm_rect_height(&s->src);
|
|
state->crtc_x = s->dst.x1;
|
|
state->crtc_y = s->dst.y1;
|
|
state->crtc_w = drm_rect_width(&s->dst);
|
|
state->crtc_h = drm_rect_height(&s->dst);
|
|
|
|
if ((state->src_x | state->src_y | state->src_w | state->src_h) &
|
|
SUBPIXEL_MASK)
|
|
return -EINVAL;
|
|
|
|
state->src_x >>= 16;
|
|
state->src_y >>= 16;
|
|
state->src_w >>= 16;
|
|
state->src_h >>= 16;
|
|
|
|
state->nplanes = fb->format->num_planes;
|
|
if (state->nplanes > ATMEL_HLCDC_LAYER_MAX_PLANES)
|
|
return -EINVAL;
|
|
|
|
hsub = drm_format_horz_chroma_subsampling(fb->format->format);
|
|
vsub = drm_format_vert_chroma_subsampling(fb->format->format);
|
|
|
|
for (i = 0; i < state->nplanes; i++) {
|
|
unsigned int offset = 0;
|
|
int xdiv = i ? hsub : 1;
|
|
int ydiv = i ? vsub : 1;
|
|
|
|
state->bpp[i] = fb->format->cpp[i];
|
|
if (!state->bpp[i])
|
|
return -EINVAL;
|
|
|
|
switch (state->base.rotation & DRM_MODE_ROTATE_MASK) {
|
|
case DRM_MODE_ROTATE_90:
|
|
offset = (state->src_y / ydiv) *
|
|
fb->pitches[i];
|
|
offset += ((state->src_x + state->src_w - 1) /
|
|
xdiv) * state->bpp[i];
|
|
state->xstride[i] = -(((state->src_h - 1) / ydiv) *
|
|
fb->pitches[i]) -
|
|
(2 * state->bpp[i]);
|
|
state->pstride[i] = fb->pitches[i] - state->bpp[i];
|
|
break;
|
|
case DRM_MODE_ROTATE_180:
|
|
offset = ((state->src_y + state->src_h - 1) /
|
|
ydiv) * fb->pitches[i];
|
|
offset += ((state->src_x + state->src_w - 1) /
|
|
xdiv) * state->bpp[i];
|
|
state->xstride[i] = ((((state->src_w - 1) / xdiv) - 1) *
|
|
state->bpp[i]) - fb->pitches[i];
|
|
state->pstride[i] = -2 * state->bpp[i];
|
|
break;
|
|
case DRM_MODE_ROTATE_270:
|
|
offset = ((state->src_y + state->src_h - 1) /
|
|
ydiv) * fb->pitches[i];
|
|
offset += (state->src_x / xdiv) * state->bpp[i];
|
|
state->xstride[i] = ((state->src_h - 1) / ydiv) *
|
|
fb->pitches[i];
|
|
state->pstride[i] = -fb->pitches[i] - state->bpp[i];
|
|
break;
|
|
case DRM_MODE_ROTATE_0:
|
|
default:
|
|
offset = (state->src_y / ydiv) * fb->pitches[i];
|
|
offset += (state->src_x / xdiv) * state->bpp[i];
|
|
state->xstride[i] = fb->pitches[i] -
|
|
((state->src_w / xdiv) *
|
|
state->bpp[i]);
|
|
state->pstride[i] = 0;
|
|
break;
|
|
}
|
|
|
|
state->offsets[i] = offset + fb->offsets[i];
|
|
}
|
|
|
|
/*
|
|
* Swap width and size in case of 90 or 270 degrees rotation
|
|
*/
|
|
if (drm_rotation_90_or_270(state->base.rotation)) {
|
|
tmp = state->src_w;
|
|
state->src_w = state->src_h;
|
|
state->src_h = tmp;
|
|
}
|
|
|
|
if (!desc->layout.size &&
|
|
(mode->hdisplay != state->crtc_w ||
|
|
mode->vdisplay != state->crtc_h))
|
|
return -EINVAL;
|
|
|
|
if ((state->crtc_h != state->src_h || state->crtc_w != state->src_w) &&
|
|
(!desc->layout.memsize ||
|
|
state->base.fb->format->has_alpha))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p,
|
|
struct drm_plane_state *old_state)
|
|
{
|
|
struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
|
|
|
|
/* Disable interrupts */
|
|
atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR,
|
|
0xffffffff);
|
|
|
|
/* Disable the layer */
|
|
atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHDR,
|
|
ATMEL_HLCDC_LAYER_RST |
|
|
ATMEL_HLCDC_LAYER_A2Q |
|
|
ATMEL_HLCDC_LAYER_UPDATE);
|
|
|
|
/* Clear all pending interrupts */
|
|
atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
|
|
}
|
|
|
|
static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,
|
|
struct drm_plane_state *old_s)
|
|
{
|
|
struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
|
|
struct atmel_hlcdc_plane_state *state =
|
|
drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
|
|
u32 sr;
|
|
|
|
if (!p->state->crtc || !p->state->fb)
|
|
return;
|
|
|
|
if (!state->base.visible) {
|
|
atmel_hlcdc_plane_atomic_disable(p, old_s);
|
|
return;
|
|
}
|
|
|
|
atmel_hlcdc_plane_update_pos_and_size(plane, state);
|
|
atmel_hlcdc_plane_update_general_settings(plane, state);
|
|
atmel_hlcdc_plane_update_format(plane, state);
|
|
atmel_hlcdc_plane_update_clut(plane, state);
|
|
atmel_hlcdc_plane_update_buffers(plane, state);
|
|
atmel_hlcdc_plane_update_disc_area(plane, state);
|
|
|
|
/* Enable the overrun interrupts. */
|
|
atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER,
|
|
ATMEL_HLCDC_LAYER_OVR_IRQ(0) |
|
|
ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
|
|
ATMEL_HLCDC_LAYER_OVR_IRQ(2));
|
|
|
|
/* Apply the new config at the next SOF event. */
|
|
sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
|
|
atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER,
|
|
ATMEL_HLCDC_LAYER_UPDATE |
|
|
(sr & ATMEL_HLCDC_LAYER_EN ?
|
|
ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN));
|
|
}
|
|
|
|
static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane)
|
|
{
|
|
const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
|
|
|
|
if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
|
|
desc->type == ATMEL_HLCDC_CURSOR_LAYER) {
|
|
int ret;
|
|
|
|
ret = drm_plane_create_alpha_property(&plane->base);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (desc->layout.xstride[0] && desc->layout.pstride[0]) {
|
|
int ret;
|
|
|
|
ret = drm_plane_create_rotation_property(&plane->base,
|
|
DRM_MODE_ROTATE_0,
|
|
DRM_MODE_ROTATE_0 |
|
|
DRM_MODE_ROTATE_90 |
|
|
DRM_MODE_ROTATE_180 |
|
|
DRM_MODE_ROTATE_270);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (desc->layout.csc) {
|
|
/*
|
|
* TODO: decare a "yuv-to-rgb-conv-factors" property to let
|
|
* userspace modify these factors (using a BLOB property ?).
|
|
*/
|
|
atmel_hlcdc_layer_write_cfg(&plane->layer,
|
|
desc->layout.csc,
|
|
0x4c900091);
|
|
atmel_hlcdc_layer_write_cfg(&plane->layer,
|
|
desc->layout.csc + 1,
|
|
0x7a5f5090);
|
|
atmel_hlcdc_layer_write_cfg(&plane->layer,
|
|
desc->layout.csc + 2,
|
|
0x40040890);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane)
|
|
{
|
|
const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
|
|
u32 isr;
|
|
|
|
isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
|
|
|
|
/*
|
|
* There's not much we can do in case of overrun except informing
|
|
* the user. However, we are in interrupt context here, hence the
|
|
* use of dev_dbg().
|
|
*/
|
|
if (isr &
|
|
(ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
|
|
ATMEL_HLCDC_LAYER_OVR_IRQ(2)))
|
|
dev_dbg(plane->base.dev->dev, "overrun on plane %s\n",
|
|
desc->name);
|
|
}
|
|
|
|
static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = {
|
|
.atomic_check = atmel_hlcdc_plane_atomic_check,
|
|
.atomic_update = atmel_hlcdc_plane_atomic_update,
|
|
.atomic_disable = atmel_hlcdc_plane_atomic_disable,
|
|
};
|
|
|
|
static int atmel_hlcdc_plane_alloc_dscrs(struct drm_plane *p,
|
|
struct atmel_hlcdc_plane_state *state)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = p->dev->dev_private;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(state->dscrs); i++) {
|
|
struct atmel_hlcdc_dma_channel_dscr *dscr;
|
|
dma_addr_t dscr_dma;
|
|
|
|
dscr = dma_pool_alloc(dc->dscrpool, GFP_KERNEL, &dscr_dma);
|
|
if (!dscr)
|
|
goto err;
|
|
|
|
dscr->addr = 0;
|
|
dscr->next = dscr_dma;
|
|
dscr->self = dscr_dma;
|
|
dscr->ctrl = ATMEL_HLCDC_LAYER_DFETCH;
|
|
|
|
state->dscrs[i] = dscr;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
for (i--; i >= 0; i--) {
|
|
dma_pool_free(dc->dscrpool, state->dscrs[i],
|
|
state->dscrs[i]->self);
|
|
}
|
|
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void atmel_hlcdc_plane_reset(struct drm_plane *p)
|
|
{
|
|
struct atmel_hlcdc_plane_state *state;
|
|
|
|
if (p->state) {
|
|
state = drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
|
|
|
|
if (state->base.fb)
|
|
drm_framebuffer_put(state->base.fb);
|
|
|
|
kfree(state);
|
|
p->state = NULL;
|
|
}
|
|
|
|
state = kzalloc(sizeof(*state), GFP_KERNEL);
|
|
if (state) {
|
|
if (atmel_hlcdc_plane_alloc_dscrs(p, state)) {
|
|
kfree(state);
|
|
dev_err(p->dev->dev,
|
|
"Failed to allocate initial plane state\n");
|
|
return;
|
|
}
|
|
__drm_atomic_helper_plane_reset(p, &state->base);
|
|
}
|
|
}
|
|
|
|
static struct drm_plane_state *
|
|
atmel_hlcdc_plane_atomic_duplicate_state(struct drm_plane *p)
|
|
{
|
|
struct atmel_hlcdc_plane_state *state =
|
|
drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
|
|
struct atmel_hlcdc_plane_state *copy;
|
|
|
|
copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
|
|
if (!copy)
|
|
return NULL;
|
|
|
|
if (atmel_hlcdc_plane_alloc_dscrs(p, copy)) {
|
|
kfree(copy);
|
|
return NULL;
|
|
}
|
|
|
|
if (copy->base.fb)
|
|
drm_framebuffer_get(copy->base.fb);
|
|
|
|
return ©->base;
|
|
}
|
|
|
|
static void atmel_hlcdc_plane_atomic_destroy_state(struct drm_plane *p,
|
|
struct drm_plane_state *s)
|
|
{
|
|
struct atmel_hlcdc_plane_state *state =
|
|
drm_plane_state_to_atmel_hlcdc_plane_state(s);
|
|
struct atmel_hlcdc_dc *dc = p->dev->dev_private;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(state->dscrs); i++) {
|
|
dma_pool_free(dc->dscrpool, state->dscrs[i],
|
|
state->dscrs[i]->self);
|
|
}
|
|
|
|
if (s->fb)
|
|
drm_framebuffer_put(s->fb);
|
|
|
|
kfree(state);
|
|
}
|
|
|
|
static const struct drm_plane_funcs layer_plane_funcs = {
|
|
.update_plane = drm_atomic_helper_update_plane,
|
|
.disable_plane = drm_atomic_helper_disable_plane,
|
|
.destroy = drm_plane_cleanup,
|
|
.reset = atmel_hlcdc_plane_reset,
|
|
.atomic_duplicate_state = atmel_hlcdc_plane_atomic_duplicate_state,
|
|
.atomic_destroy_state = atmel_hlcdc_plane_atomic_destroy_state,
|
|
};
|
|
|
|
static int atmel_hlcdc_plane_create(struct drm_device *dev,
|
|
const struct atmel_hlcdc_layer_desc *desc)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
struct atmel_hlcdc_plane *plane;
|
|
enum drm_plane_type type;
|
|
int ret;
|
|
|
|
plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL);
|
|
if (!plane)
|
|
return -ENOMEM;
|
|
|
|
atmel_hlcdc_layer_init(&plane->layer, desc, dc->hlcdc->regmap);
|
|
|
|
if (desc->type == ATMEL_HLCDC_BASE_LAYER)
|
|
type = DRM_PLANE_TYPE_PRIMARY;
|
|
else if (desc->type == ATMEL_HLCDC_CURSOR_LAYER)
|
|
type = DRM_PLANE_TYPE_CURSOR;
|
|
else
|
|
type = DRM_PLANE_TYPE_OVERLAY;
|
|
|
|
ret = drm_universal_plane_init(dev, &plane->base, 0,
|
|
&layer_plane_funcs,
|
|
desc->formats->formats,
|
|
desc->formats->nformats,
|
|
NULL, type, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
drm_plane_helper_add(&plane->base,
|
|
&atmel_hlcdc_layer_plane_helper_funcs);
|
|
|
|
/* Set default property values*/
|
|
ret = atmel_hlcdc_plane_init_properties(plane);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dc->layers[desc->id] = &plane->layer;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int atmel_hlcdc_create_planes(struct drm_device *dev)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers;
|
|
int nlayers = dc->desc->nlayers;
|
|
int i, ret;
|
|
|
|
dc->dscrpool = dmam_pool_create("atmel-hlcdc-dscr", dev->dev,
|
|
sizeof(struct atmel_hlcdc_dma_channel_dscr),
|
|
sizeof(u64), 0);
|
|
if (!dc->dscrpool)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < nlayers; i++) {
|
|
if (descs[i].type != ATMEL_HLCDC_BASE_LAYER &&
|
|
descs[i].type != ATMEL_HLCDC_OVERLAY_LAYER &&
|
|
descs[i].type != ATMEL_HLCDC_CURSOR_LAYER)
|
|
continue;
|
|
|
|
ret = atmel_hlcdc_plane_create(dev, &descs[i]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|