f9a2348196
The Amlogic Meson GX SoCs support an Overlay plane behind the primary plane for video rendering. This Overlay plane support various YUV layouts : - YUYV - NV12 / NV21 - YUV444 / 422 / 420 / 411 / 410 The scaler supports a wide range of scaling ratios, but for simplicity, plane atomic check limits the scaling from x5 to /5 in vertical and horizontal scaling. The z-order is fixed and always behind the primary plane and cannot be changed. The scaling parameter algorithm was taken from the Amlogic vendor kernel code and rewritten to match the atomic universal plane requirements. The video rendering using this overlay plane support has been tested using the new Kodi DRM-KMS Prime rendering path along the in-review V4L2 Mem2Mem Hardware Video Decoder up to 3840x2160 NV12 frames on various display modes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Tested-by: Maxime Jourdan <mjourdan@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/1541497202-20570-2-git-send-email-narmstrong@baylibre.com
74 lines
2.3 KiB
C
74 lines
2.3 KiB
C
/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include "meson_drv.h"
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#include "meson_canvas.h"
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#include "meson_registers.h"
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/**
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* DOC: Canvas
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*
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* CANVAS is a memory zone where physical memory frames information
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* are stored for the VIU to scanout.
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*/
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/* DMC Registers */
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#define DMC_CAV_LUT_DATAL 0x48 /* 0x12 offset in data sheet */
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#define CANVAS_WIDTH_LBIT 29
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#define CANVAS_WIDTH_LWID 3
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#define DMC_CAV_LUT_DATAH 0x4c /* 0x13 offset in data sheet */
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#define CANVAS_WIDTH_HBIT 0
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#define CANVAS_HEIGHT_BIT 9
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#define CANVAS_BLKMODE_BIT 24
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#define CANVAS_ENDIAN_BIT 26
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#define DMC_CAV_LUT_ADDR 0x50 /* 0x14 offset in data sheet */
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#define CANVAS_LUT_WR_EN (0x2 << 8)
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#define CANVAS_LUT_RD_EN (0x1 << 8)
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void meson_canvas_setup(struct meson_drm *priv,
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uint32_t canvas_index, uint32_t addr,
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uint32_t stride, uint32_t height,
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unsigned int wrap,
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unsigned int blkmode,
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unsigned int endian)
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{
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unsigned int val;
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regmap_write(priv->dmc, DMC_CAV_LUT_DATAL,
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(((addr + 7) >> 3)) |
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(((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
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regmap_write(priv->dmc, DMC_CAV_LUT_DATAH,
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((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) <<
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CANVAS_WIDTH_HBIT) |
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(height << CANVAS_HEIGHT_BIT) |
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(wrap << 22) |
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(blkmode << CANVAS_BLKMODE_BIT) |
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(endian << CANVAS_ENDIAN_BIT));
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regmap_write(priv->dmc, DMC_CAV_LUT_ADDR,
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CANVAS_LUT_WR_EN | canvas_index);
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/* Force a read-back to make sure everything is flushed. */
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regmap_read(priv->dmc, DMC_CAV_LUT_DATAH, &val);
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}
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