![Christian König](/assets/img/avatar_default.png)
Let's support simultaneous submissions to multiple engines. v2: rename the field to num_shared and fix up all users v3: rebased Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1269 lines
32 KiB
C
1269 lines
32 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "radeon_trace.h"
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/*
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* GPUVM
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* GPUVM is similar to the legacy gart on older asics, however
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* rather than there being a single global gart table
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* for the entire GPU, there are multiple VM page tables active
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* at any given time. The VM page tables can contain a mix
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* vram pages and system memory pages and system memory pages
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* can be mapped as snooped (cached system pages) or unsnooped
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* (uncached system pages).
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* Each VM has an ID associated with it and there is a page table
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* associated with each VMID. When execting a command buffer,
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* the kernel tells the the ring what VMID to use for that command
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* buffer. VMIDs are allocated dynamically as commands are submitted.
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* The userspace drivers maintain their own address space and the kernel
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* sets up their pages tables accordingly when they submit their
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* command buffers and a VMID is assigned.
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* Cayman/Trinity support up to 8 active VMs at any given time;
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* SI supports 16.
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*/
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/**
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* radeon_vm_num_pde - return the number of page directory entries
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*
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* @rdev: radeon_device pointer
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*
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* Calculate the number of page directory entries (cayman+).
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*/
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static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
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{
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return rdev->vm_manager.max_pfn >> radeon_vm_block_size;
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}
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/**
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* radeon_vm_directory_size - returns the size of the page directory in bytes
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*
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* @rdev: radeon_device pointer
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*
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* Calculate the size of the page directory in bytes (cayman+).
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*/
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static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
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{
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return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
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}
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/**
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* radeon_vm_manager_init - init the vm manager
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*
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* @rdev: radeon_device pointer
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*
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* Init the vm manager (cayman+).
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* Returns 0 for success, error for failure.
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*/
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int radeon_vm_manager_init(struct radeon_device *rdev)
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{
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int r;
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if (!rdev->vm_manager.enabled) {
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r = radeon_asic_vm_init(rdev);
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if (r)
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return r;
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rdev->vm_manager.enabled = true;
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}
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return 0;
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}
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/**
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* radeon_vm_manager_fini - tear down the vm manager
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*
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* @rdev: radeon_device pointer
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*
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* Tear down the VM manager (cayman+).
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*/
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void radeon_vm_manager_fini(struct radeon_device *rdev)
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{
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int i;
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if (!rdev->vm_manager.enabled)
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return;
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for (i = 0; i < RADEON_NUM_VM; ++i)
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radeon_fence_unref(&rdev->vm_manager.active[i]);
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radeon_asic_vm_fini(rdev);
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rdev->vm_manager.enabled = false;
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}
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/**
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* radeon_vm_get_bos - add the vm BOs to a validation list
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*
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* @vm: vm providing the BOs
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* @head: head of validation list
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*
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* Add the page directory to the list of BOs to
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* validate for command submission (cayman+).
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*/
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struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
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struct radeon_vm *vm,
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struct list_head *head)
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{
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struct radeon_bo_list *list;
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unsigned i, idx;
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list = kvmalloc_array(vm->max_pde_used + 2,
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sizeof(struct radeon_bo_list), GFP_KERNEL);
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if (!list)
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return NULL;
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/* add the vm page table to the list */
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list[0].robj = vm->page_directory;
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list[0].preferred_domains = RADEON_GEM_DOMAIN_VRAM;
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list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
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list[0].tv.bo = &vm->page_directory->tbo;
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list[0].tv.num_shared = 1;
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list[0].tiling_flags = 0;
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list_add(&list[0].tv.head, head);
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for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
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if (!vm->page_tables[i].bo)
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continue;
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list[idx].robj = vm->page_tables[i].bo;
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list[idx].preferred_domains = RADEON_GEM_DOMAIN_VRAM;
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list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM;
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list[idx].tv.bo = &list[idx].robj->tbo;
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list[idx].tv.num_shared = 1;
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list[idx].tiling_flags = 0;
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list_add(&list[idx++].tv.head, head);
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}
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return list;
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}
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/**
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* radeon_vm_grab_id - allocate the next free VMID
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*
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* @rdev: radeon_device pointer
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* @vm: vm to allocate id for
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* @ring: ring we want to submit job to
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*
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* Allocate an id for the vm (cayman+).
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* Returns the fence we need to sync to (if any).
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*
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* Global and local mutex must be locked!
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*/
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struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
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struct radeon_vm *vm, int ring)
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{
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struct radeon_fence *best[RADEON_NUM_RINGS] = {};
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struct radeon_vm_id *vm_id = &vm->ids[ring];
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unsigned choices[2] = {};
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unsigned i;
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/* check if the id is still valid */
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if (vm_id->id && vm_id->last_id_use &&
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vm_id->last_id_use == rdev->vm_manager.active[vm_id->id])
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return NULL;
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/* we definately need to flush */
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vm_id->pd_gpu_addr = ~0ll;
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/* skip over VMID 0, since it is the system VM */
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for (i = 1; i < rdev->vm_manager.nvm; ++i) {
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struct radeon_fence *fence = rdev->vm_manager.active[i];
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if (fence == NULL) {
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/* found a free one */
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vm_id->id = i;
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trace_radeon_vm_grab_id(i, ring);
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return NULL;
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}
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if (radeon_fence_is_earlier(fence, best[fence->ring])) {
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best[fence->ring] = fence;
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choices[fence->ring == ring ? 0 : 1] = i;
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}
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}
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for (i = 0; i < 2; ++i) {
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if (choices[i]) {
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vm_id->id = choices[i];
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trace_radeon_vm_grab_id(choices[i], ring);
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return rdev->vm_manager.active[choices[i]];
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}
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}
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/* should never happen */
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BUG();
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return NULL;
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}
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/**
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* radeon_vm_flush - hardware flush the vm
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*
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* @rdev: radeon_device pointer
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* @vm: vm we want to flush
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* @ring: ring to use for flush
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* @updates: last vm update that is waited for
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*
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* Flush the vm (cayman+).
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*
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* Global and local mutex must be locked!
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*/
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void radeon_vm_flush(struct radeon_device *rdev,
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struct radeon_vm *vm,
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int ring, struct radeon_fence *updates)
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{
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uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
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struct radeon_vm_id *vm_id = &vm->ids[ring];
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if (pd_addr != vm_id->pd_gpu_addr || !vm_id->flushed_updates ||
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radeon_fence_is_earlier(vm_id->flushed_updates, updates)) {
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trace_radeon_vm_flush(pd_addr, ring, vm->ids[ring].id);
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radeon_fence_unref(&vm_id->flushed_updates);
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vm_id->flushed_updates = radeon_fence_ref(updates);
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vm_id->pd_gpu_addr = pd_addr;
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radeon_ring_vm_flush(rdev, &rdev->ring[ring],
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vm_id->id, vm_id->pd_gpu_addr);
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}
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}
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/**
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* radeon_vm_fence - remember fence for vm
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*
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* @rdev: radeon_device pointer
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* @vm: vm we want to fence
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* @fence: fence to remember
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*
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* Fence the vm (cayman+).
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* Set the fence used to protect page table and id.
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*
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* Global and local mutex must be locked!
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*/
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void radeon_vm_fence(struct radeon_device *rdev,
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struct radeon_vm *vm,
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struct radeon_fence *fence)
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{
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unsigned vm_id = vm->ids[fence->ring].id;
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radeon_fence_unref(&rdev->vm_manager.active[vm_id]);
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rdev->vm_manager.active[vm_id] = radeon_fence_ref(fence);
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radeon_fence_unref(&vm->ids[fence->ring].last_id_use);
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vm->ids[fence->ring].last_id_use = radeon_fence_ref(fence);
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}
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/**
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* radeon_vm_bo_find - find the bo_va for a specific vm & bo
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*
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* @vm: requested vm
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* @bo: requested buffer object
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*
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* Find @bo inside the requested vm (cayman+).
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* Search inside the @bos vm list for the requested vm
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* Returns the found bo_va or NULL if none is found
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*
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* Object has to be reserved!
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*/
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struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
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struct radeon_bo *bo)
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{
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struct radeon_bo_va *bo_va;
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list_for_each_entry(bo_va, &bo->va, bo_list) {
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if (bo_va->vm == vm) {
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return bo_va;
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}
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}
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return NULL;
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}
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/**
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* radeon_vm_bo_add - add a bo to a specific vm
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*
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* @rdev: radeon_device pointer
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* @vm: requested vm
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* @bo: radeon buffer object
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*
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* Add @bo into the requested vm (cayman+).
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* Add @bo to the list of bos associated with the vm
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* Returns newly added bo_va or NULL for failure
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*
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* Object has to be reserved!
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*/
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struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
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struct radeon_vm *vm,
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struct radeon_bo *bo)
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{
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struct radeon_bo_va *bo_va;
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bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
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if (bo_va == NULL) {
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return NULL;
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}
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bo_va->vm = vm;
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bo_va->bo = bo;
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bo_va->it.start = 0;
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bo_va->it.last = 0;
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bo_va->flags = 0;
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bo_va->ref_count = 1;
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INIT_LIST_HEAD(&bo_va->bo_list);
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INIT_LIST_HEAD(&bo_va->vm_status);
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mutex_lock(&vm->mutex);
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list_add_tail(&bo_va->bo_list, &bo->va);
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mutex_unlock(&vm->mutex);
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return bo_va;
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}
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/**
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* radeon_vm_set_pages - helper to call the right asic function
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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*
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* Traces the parameters and calls the right asic functions
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* to setup the page table using the DMA.
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*/
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static void radeon_vm_set_pages(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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{
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trace_radeon_vm_set_page(pe, addr, count, incr, flags);
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if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
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uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
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radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);
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} else if ((flags & R600_PTE_SYSTEM) || (count < 3)) {
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radeon_asic_vm_write_pages(rdev, ib, pe, addr,
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count, incr, flags);
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} else {
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radeon_asic_vm_set_pages(rdev, ib, pe, addr,
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count, incr, flags);
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}
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}
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/**
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* radeon_vm_clear_bo - initially clear the page dir/table
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*
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* @rdev: radeon_device pointer
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* @bo: bo to clear
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*/
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static int radeon_vm_clear_bo(struct radeon_device *rdev,
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struct radeon_bo *bo)
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{
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struct ttm_operation_ctx ctx = { true, false };
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struct radeon_ib ib;
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unsigned entries;
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uint64_t addr;
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int r;
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r = radeon_bo_reserve(bo, false);
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if (r)
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return r;
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r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
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if (r)
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goto error_unreserve;
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addr = radeon_bo_gpu_offset(bo);
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entries = radeon_bo_size(bo) / 8;
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r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256);
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if (r)
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goto error_unreserve;
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ib.length_dw = 0;
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radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0);
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radeon_asic_vm_pad_ib(rdev, &ib);
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WARN_ON(ib.length_dw > 64);
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r = radeon_ib_schedule(rdev, &ib, NULL, false);
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if (r)
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goto error_free;
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ib.fence->is_vm_update = true;
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radeon_bo_fence(bo, ib.fence, false);
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error_free:
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radeon_ib_free(rdev, &ib);
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error_unreserve:
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radeon_bo_unreserve(bo);
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return r;
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}
|
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|
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/**
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* radeon_vm_bo_set_addr - set bos virtual address inside a vm
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*
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* @rdev: radeon_device pointer
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* @bo_va: bo_va to store the address
|
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* @soffset: requested offset of the buffer in the VM address space
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* @flags: attributes of pages (read/write/valid/etc.)
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*
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* Set offset of @bo_va (cayman+).
|
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* Validate and set the offset requested within the vm address space.
|
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* Returns 0 for success, error for failure.
|
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*
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* Object has to be reserved and gets unreserved by this function!
|
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*/
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int radeon_vm_bo_set_addr(struct radeon_device *rdev,
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struct radeon_bo_va *bo_va,
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uint64_t soffset,
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uint32_t flags)
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{
|
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uint64_t size = radeon_bo_size(bo_va->bo);
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struct radeon_vm *vm = bo_va->vm;
|
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unsigned last_pfn, pt_idx;
|
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uint64_t eoffset;
|
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int r;
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|
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if (soffset) {
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/* make sure object fit at this offset */
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eoffset = soffset + size - 1;
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if (soffset >= eoffset) {
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r = -EINVAL;
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goto error_unreserve;
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}
|
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|
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last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
|
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if (last_pfn >= rdev->vm_manager.max_pfn) {
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dev_err(rdev->dev, "va above limit (0x%08X >= 0x%08X)\n",
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last_pfn, rdev->vm_manager.max_pfn);
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r = -EINVAL;
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goto error_unreserve;
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}
|
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|
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} else {
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eoffset = last_pfn = 0;
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}
|
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|
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mutex_lock(&vm->mutex);
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soffset /= RADEON_GPU_PAGE_SIZE;
|
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eoffset /= RADEON_GPU_PAGE_SIZE;
|
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if (soffset || eoffset) {
|
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struct interval_tree_node *it;
|
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it = interval_tree_iter_first(&vm->va, soffset, eoffset);
|
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if (it && it != &bo_va->it) {
|
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struct radeon_bo_va *tmp;
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tmp = container_of(it, struct radeon_bo_va, it);
|
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/* bo and tmp overlap, invalid offset */
|
|
dev_err(rdev->dev, "bo %p va 0x%010Lx conflict with "
|
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"(bo %p 0x%010lx 0x%010lx)\n", bo_va->bo,
|
|
soffset, tmp->bo, tmp->it.start, tmp->it.last);
|
|
mutex_unlock(&vm->mutex);
|
|
r = -EINVAL;
|
|
goto error_unreserve;
|
|
}
|
|
}
|
|
|
|
if (bo_va->it.start || bo_va->it.last) {
|
|
/* add a clone of the bo_va to clear the old address */
|
|
struct radeon_bo_va *tmp;
|
|
tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
|
|
if (!tmp) {
|
|
mutex_unlock(&vm->mutex);
|
|
r = -ENOMEM;
|
|
goto error_unreserve;
|
|
}
|
|
tmp->it.start = bo_va->it.start;
|
|
tmp->it.last = bo_va->it.last;
|
|
tmp->vm = vm;
|
|
tmp->bo = radeon_bo_ref(bo_va->bo);
|
|
|
|
interval_tree_remove(&bo_va->it, &vm->va);
|
|
spin_lock(&vm->status_lock);
|
|
bo_va->it.start = 0;
|
|
bo_va->it.last = 0;
|
|
list_del_init(&bo_va->vm_status);
|
|
list_add(&tmp->vm_status, &vm->freed);
|
|
spin_unlock(&vm->status_lock);
|
|
}
|
|
|
|
if (soffset || eoffset) {
|
|
spin_lock(&vm->status_lock);
|
|
bo_va->it.start = soffset;
|
|
bo_va->it.last = eoffset;
|
|
list_add(&bo_va->vm_status, &vm->cleared);
|
|
spin_unlock(&vm->status_lock);
|
|
interval_tree_insert(&bo_va->it, &vm->va);
|
|
}
|
|
|
|
bo_va->flags = flags;
|
|
|
|
soffset >>= radeon_vm_block_size;
|
|
eoffset >>= radeon_vm_block_size;
|
|
|
|
BUG_ON(eoffset >= radeon_vm_num_pdes(rdev));
|
|
|
|
if (eoffset > vm->max_pde_used)
|
|
vm->max_pde_used = eoffset;
|
|
|
|
radeon_bo_unreserve(bo_va->bo);
|
|
|
|
/* walk over the address space and allocate the page tables */
|
|
for (pt_idx = soffset; pt_idx <= eoffset; ++pt_idx) {
|
|
struct radeon_bo *pt;
|
|
|
|
if (vm->page_tables[pt_idx].bo)
|
|
continue;
|
|
|
|
/* drop mutex to allocate and clear page table */
|
|
mutex_unlock(&vm->mutex);
|
|
|
|
r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
|
|
RADEON_GPU_PAGE_SIZE, true,
|
|
RADEON_GEM_DOMAIN_VRAM, 0,
|
|
NULL, NULL, &pt);
|
|
if (r)
|
|
return r;
|
|
|
|
r = radeon_vm_clear_bo(rdev, pt);
|
|
if (r) {
|
|
radeon_bo_unref(&pt);
|
|
return r;
|
|
}
|
|
|
|
/* aquire mutex again */
|
|
mutex_lock(&vm->mutex);
|
|
if (vm->page_tables[pt_idx].bo) {
|
|
/* someone else allocated the pt in the meantime */
|
|
mutex_unlock(&vm->mutex);
|
|
radeon_bo_unref(&pt);
|
|
mutex_lock(&vm->mutex);
|
|
continue;
|
|
}
|
|
|
|
vm->page_tables[pt_idx].addr = 0;
|
|
vm->page_tables[pt_idx].bo = pt;
|
|
}
|
|
|
|
mutex_unlock(&vm->mutex);
|
|
return 0;
|
|
|
|
error_unreserve:
|
|
radeon_bo_unreserve(bo_va->bo);
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_map_gart - get the physical address of a gart page
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @addr: the unmapped addr
|
|
*
|
|
* Look up the physical address of the page that the pte resolves
|
|
* to (cayman+).
|
|
* Returns the physical address of the page.
|
|
*/
|
|
uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
|
|
{
|
|
uint64_t result;
|
|
|
|
/* page table offset */
|
|
result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT];
|
|
result &= ~RADEON_GPU_PAGE_MASK;
|
|
|
|
return result;
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_page_flags - translate page flags to what the hw uses
|
|
*
|
|
* @flags: flags comming from userspace
|
|
*
|
|
* Translate the flags the userspace ABI uses to hw flags.
|
|
*/
|
|
static uint32_t radeon_vm_page_flags(uint32_t flags)
|
|
{
|
|
uint32_t hw_flags = 0;
|
|
|
|
hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
|
|
hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
|
|
hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
|
|
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
|
hw_flags |= R600_PTE_SYSTEM;
|
|
hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
|
|
}
|
|
return hw_flags;
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_update_pdes - make sure that page directory is valid
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @vm: requested vm
|
|
* @start: start of GPU address range
|
|
* @end: end of GPU address range
|
|
*
|
|
* Allocates new page tables if necessary
|
|
* and updates the page directory (cayman+).
|
|
* Returns 0 for success, error for failure.
|
|
*
|
|
* Global and local mutex must be locked!
|
|
*/
|
|
int radeon_vm_update_page_directory(struct radeon_device *rdev,
|
|
struct radeon_vm *vm)
|
|
{
|
|
struct radeon_bo *pd = vm->page_directory;
|
|
uint64_t pd_addr = radeon_bo_gpu_offset(pd);
|
|
uint32_t incr = RADEON_VM_PTE_COUNT * 8;
|
|
uint64_t last_pde = ~0, last_pt = ~0;
|
|
unsigned count = 0, pt_idx, ndw;
|
|
struct radeon_ib ib;
|
|
int r;
|
|
|
|
/* padding, etc. */
|
|
ndw = 64;
|
|
|
|
/* assume the worst case */
|
|
ndw += vm->max_pde_used * 6;
|
|
|
|
/* update too big for an IB */
|
|
if (ndw > 0xfffff)
|
|
return -ENOMEM;
|
|
|
|
r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
|
|
if (r)
|
|
return r;
|
|
ib.length_dw = 0;
|
|
|
|
/* walk over the address space and update the page directory */
|
|
for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
|
|
struct radeon_bo *bo = vm->page_tables[pt_idx].bo;
|
|
uint64_t pde, pt;
|
|
|
|
if (bo == NULL)
|
|
continue;
|
|
|
|
pt = radeon_bo_gpu_offset(bo);
|
|
if (vm->page_tables[pt_idx].addr == pt)
|
|
continue;
|
|
vm->page_tables[pt_idx].addr = pt;
|
|
|
|
pde = pd_addr + pt_idx * 8;
|
|
if (((last_pde + 8 * count) != pde) ||
|
|
((last_pt + incr * count) != pt)) {
|
|
|
|
if (count) {
|
|
radeon_vm_set_pages(rdev, &ib, last_pde,
|
|
last_pt, count, incr,
|
|
R600_PTE_VALID);
|
|
}
|
|
|
|
count = 1;
|
|
last_pde = pde;
|
|
last_pt = pt;
|
|
} else {
|
|
++count;
|
|
}
|
|
}
|
|
|
|
if (count)
|
|
radeon_vm_set_pages(rdev, &ib, last_pde, last_pt, count,
|
|
incr, R600_PTE_VALID);
|
|
|
|
if (ib.length_dw != 0) {
|
|
radeon_asic_vm_pad_ib(rdev, &ib);
|
|
|
|
radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, true);
|
|
WARN_ON(ib.length_dw > ndw);
|
|
r = radeon_ib_schedule(rdev, &ib, NULL, false);
|
|
if (r) {
|
|
radeon_ib_free(rdev, &ib);
|
|
return r;
|
|
}
|
|
ib.fence->is_vm_update = true;
|
|
radeon_bo_fence(pd, ib.fence, false);
|
|
}
|
|
radeon_ib_free(rdev, &ib);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_frag_ptes - add fragment information to PTEs
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @ib: IB for the update
|
|
* @pe_start: first PTE to handle
|
|
* @pe_end: last PTE to handle
|
|
* @addr: addr those PTEs should point to
|
|
* @flags: hw mapping flags
|
|
*
|
|
* Global and local mutex must be locked!
|
|
*/
|
|
static void radeon_vm_frag_ptes(struct radeon_device *rdev,
|
|
struct radeon_ib *ib,
|
|
uint64_t pe_start, uint64_t pe_end,
|
|
uint64_t addr, uint32_t flags)
|
|
{
|
|
/**
|
|
* The MC L1 TLB supports variable sized pages, based on a fragment
|
|
* field in the PTE. When this field is set to a non-zero value, page
|
|
* granularity is increased from 4KB to (1 << (12 + frag)). The PTE
|
|
* flags are considered valid for all PTEs within the fragment range
|
|
* and corresponding mappings are assumed to be physically contiguous.
|
|
*
|
|
* The L1 TLB can store a single PTE for the whole fragment,
|
|
* significantly increasing the space available for translation
|
|
* caching. This leads to large improvements in throughput when the
|
|
* TLB is under pressure.
|
|
*
|
|
* The L2 TLB distributes small and large fragments into two
|
|
* asymmetric partitions. The large fragment cache is significantly
|
|
* larger. Thus, we try to use large fragments wherever possible.
|
|
* Userspace can support this by aligning virtual base address and
|
|
* allocation size to the fragment size.
|
|
*/
|
|
|
|
/* NI is optimized for 256KB fragments, SI and newer for 64KB */
|
|
uint64_t frag_flags = ((rdev->family == CHIP_CAYMAN) ||
|
|
(rdev->family == CHIP_ARUBA)) ?
|
|
R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB;
|
|
uint64_t frag_align = ((rdev->family == CHIP_CAYMAN) ||
|
|
(rdev->family == CHIP_ARUBA)) ? 0x200 : 0x80;
|
|
|
|
uint64_t frag_start = ALIGN(pe_start, frag_align);
|
|
uint64_t frag_end = pe_end & ~(frag_align - 1);
|
|
|
|
unsigned count;
|
|
|
|
/* system pages are non continuously */
|
|
if ((flags & R600_PTE_SYSTEM) || !(flags & R600_PTE_VALID) ||
|
|
(frag_start >= frag_end)) {
|
|
|
|
count = (pe_end - pe_start) / 8;
|
|
radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
|
|
RADEON_GPU_PAGE_SIZE, flags);
|
|
return;
|
|
}
|
|
|
|
/* handle the 4K area at the beginning */
|
|
if (pe_start != frag_start) {
|
|
count = (frag_start - pe_start) / 8;
|
|
radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
|
|
RADEON_GPU_PAGE_SIZE, flags);
|
|
addr += RADEON_GPU_PAGE_SIZE * count;
|
|
}
|
|
|
|
/* handle the area in the middle */
|
|
count = (frag_end - frag_start) / 8;
|
|
radeon_vm_set_pages(rdev, ib, frag_start, addr, count,
|
|
RADEON_GPU_PAGE_SIZE, flags | frag_flags);
|
|
|
|
/* handle the 4K area at the end */
|
|
if (frag_end != pe_end) {
|
|
addr += RADEON_GPU_PAGE_SIZE * count;
|
|
count = (pe_end - frag_end) / 8;
|
|
radeon_vm_set_pages(rdev, ib, frag_end, addr, count,
|
|
RADEON_GPU_PAGE_SIZE, flags);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_update_ptes - make sure that page tables are valid
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @vm: requested vm
|
|
* @start: start of GPU address range
|
|
* @end: end of GPU address range
|
|
* @dst: destination address to map to
|
|
* @flags: mapping flags
|
|
*
|
|
* Update the page tables in the range @start - @end (cayman+).
|
|
*
|
|
* Global and local mutex must be locked!
|
|
*/
|
|
static int radeon_vm_update_ptes(struct radeon_device *rdev,
|
|
struct radeon_vm *vm,
|
|
struct radeon_ib *ib,
|
|
uint64_t start, uint64_t end,
|
|
uint64_t dst, uint32_t flags)
|
|
{
|
|
uint64_t mask = RADEON_VM_PTE_COUNT - 1;
|
|
uint64_t last_pte = ~0, last_dst = ~0;
|
|
unsigned count = 0;
|
|
uint64_t addr;
|
|
|
|
/* walk over the address space and update the page tables */
|
|
for (addr = start; addr < end; ) {
|
|
uint64_t pt_idx = addr >> radeon_vm_block_size;
|
|
struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
|
|
unsigned nptes;
|
|
uint64_t pte;
|
|
int r;
|
|
|
|
radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, true);
|
|
r = reservation_object_reserve_shared(pt->tbo.resv, 1);
|
|
if (r)
|
|
return r;
|
|
|
|
if ((addr & ~mask) == (end & ~mask))
|
|
nptes = end - addr;
|
|
else
|
|
nptes = RADEON_VM_PTE_COUNT - (addr & mask);
|
|
|
|
pte = radeon_bo_gpu_offset(pt);
|
|
pte += (addr & mask) * 8;
|
|
|
|
if ((last_pte + 8 * count) != pte) {
|
|
|
|
if (count) {
|
|
radeon_vm_frag_ptes(rdev, ib, last_pte,
|
|
last_pte + 8 * count,
|
|
last_dst, flags);
|
|
}
|
|
|
|
count = nptes;
|
|
last_pte = pte;
|
|
last_dst = dst;
|
|
} else {
|
|
count += nptes;
|
|
}
|
|
|
|
addr += nptes;
|
|
dst += nptes * RADEON_GPU_PAGE_SIZE;
|
|
}
|
|
|
|
if (count) {
|
|
radeon_vm_frag_ptes(rdev, ib, last_pte,
|
|
last_pte + 8 * count,
|
|
last_dst, flags);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_fence_pts - fence page tables after an update
|
|
*
|
|
* @vm: requested vm
|
|
* @start: start of GPU address range
|
|
* @end: end of GPU address range
|
|
* @fence: fence to use
|
|
*
|
|
* Fence the page tables in the range @start - @end (cayman+).
|
|
*
|
|
* Global and local mutex must be locked!
|
|
*/
|
|
static void radeon_vm_fence_pts(struct radeon_vm *vm,
|
|
uint64_t start, uint64_t end,
|
|
struct radeon_fence *fence)
|
|
{
|
|
unsigned i;
|
|
|
|
start >>= radeon_vm_block_size;
|
|
end = (end - 1) >> radeon_vm_block_size;
|
|
|
|
for (i = start; i <= end; ++i)
|
|
radeon_bo_fence(vm->page_tables[i].bo, fence, true);
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_bo_update - map a bo into the vm page table
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @vm: requested vm
|
|
* @bo: radeon buffer object
|
|
* @mem: ttm mem
|
|
*
|
|
* Fill in the page table entries for @bo (cayman+).
|
|
* Returns 0 for success, -EINVAL for failure.
|
|
*
|
|
* Object have to be reserved and mutex must be locked!
|
|
*/
|
|
int radeon_vm_bo_update(struct radeon_device *rdev,
|
|
struct radeon_bo_va *bo_va,
|
|
struct ttm_mem_reg *mem)
|
|
{
|
|
struct radeon_vm *vm = bo_va->vm;
|
|
struct radeon_ib ib;
|
|
unsigned nptes, ncmds, ndw;
|
|
uint64_t addr;
|
|
uint32_t flags;
|
|
int r;
|
|
|
|
if (!bo_va->it.start) {
|
|
dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
|
|
bo_va->bo, vm);
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock(&vm->status_lock);
|
|
if (mem) {
|
|
if (list_empty(&bo_va->vm_status)) {
|
|
spin_unlock(&vm->status_lock);
|
|
return 0;
|
|
}
|
|
list_del_init(&bo_va->vm_status);
|
|
} else {
|
|
list_del(&bo_va->vm_status);
|
|
list_add(&bo_va->vm_status, &vm->cleared);
|
|
}
|
|
spin_unlock(&vm->status_lock);
|
|
|
|
bo_va->flags &= ~RADEON_VM_PAGE_VALID;
|
|
bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
|
|
bo_va->flags &= ~RADEON_VM_PAGE_SNOOPED;
|
|
if (bo_va->bo && radeon_ttm_tt_is_readonly(bo_va->bo->tbo.ttm))
|
|
bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE;
|
|
|
|
if (mem) {
|
|
addr = (u64)mem->start << PAGE_SHIFT;
|
|
if (mem->mem_type != TTM_PL_SYSTEM) {
|
|
bo_va->flags |= RADEON_VM_PAGE_VALID;
|
|
}
|
|
if (mem->mem_type == TTM_PL_TT) {
|
|
bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
|
|
if (!(bo_va->bo->flags & (RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC)))
|
|
bo_va->flags |= RADEON_VM_PAGE_SNOOPED;
|
|
|
|
} else {
|
|
addr += rdev->vm_manager.vram_base_offset;
|
|
}
|
|
} else {
|
|
addr = 0;
|
|
}
|
|
|
|
trace_radeon_vm_bo_update(bo_va);
|
|
|
|
nptes = bo_va->it.last - bo_va->it.start + 1;
|
|
|
|
/* reserve space for one command every (1 << BLOCK_SIZE) entries
|
|
or 2k dwords (whatever is smaller) */
|
|
ncmds = (nptes >> min(radeon_vm_block_size, 11)) + 1;
|
|
|
|
/* padding, etc. */
|
|
ndw = 64;
|
|
|
|
flags = radeon_vm_page_flags(bo_va->flags);
|
|
if ((flags & R600_PTE_GART_MASK) == R600_PTE_GART_MASK) {
|
|
/* only copy commands needed */
|
|
ndw += ncmds * 7;
|
|
|
|
} else if (flags & R600_PTE_SYSTEM) {
|
|
/* header for write data commands */
|
|
ndw += ncmds * 4;
|
|
|
|
/* body of write data command */
|
|
ndw += nptes * 2;
|
|
|
|
} else {
|
|
/* set page commands needed */
|
|
ndw += ncmds * 10;
|
|
|
|
/* two extra commands for begin/end of fragment */
|
|
ndw += 2 * 10;
|
|
}
|
|
|
|
/* update too big for an IB */
|
|
if (ndw > 0xfffff)
|
|
return -ENOMEM;
|
|
|
|
r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, ndw * 4);
|
|
if (r)
|
|
return r;
|
|
ib.length_dw = 0;
|
|
|
|
if (!(bo_va->flags & RADEON_VM_PAGE_VALID)) {
|
|
unsigned i;
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i)
|
|
radeon_sync_fence(&ib.sync, vm->ids[i].last_id_use);
|
|
}
|
|
|
|
r = radeon_vm_update_ptes(rdev, vm, &ib, bo_va->it.start,
|
|
bo_va->it.last + 1, addr,
|
|
radeon_vm_page_flags(bo_va->flags));
|
|
if (r) {
|
|
radeon_ib_free(rdev, &ib);
|
|
return r;
|
|
}
|
|
|
|
radeon_asic_vm_pad_ib(rdev, &ib);
|
|
WARN_ON(ib.length_dw > ndw);
|
|
|
|
r = radeon_ib_schedule(rdev, &ib, NULL, false);
|
|
if (r) {
|
|
radeon_ib_free(rdev, &ib);
|
|
return r;
|
|
}
|
|
ib.fence->is_vm_update = true;
|
|
radeon_vm_fence_pts(vm, bo_va->it.start, bo_va->it.last + 1, ib.fence);
|
|
radeon_fence_unref(&bo_va->last_pt_update);
|
|
bo_va->last_pt_update = radeon_fence_ref(ib.fence);
|
|
radeon_ib_free(rdev, &ib);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_clear_freed - clear freed BOs in the PT
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @vm: requested vm
|
|
*
|
|
* Make sure all freed BOs are cleared in the PT.
|
|
* Returns 0 for success.
|
|
*
|
|
* PTs have to be reserved and mutex must be locked!
|
|
*/
|
|
int radeon_vm_clear_freed(struct radeon_device *rdev,
|
|
struct radeon_vm *vm)
|
|
{
|
|
struct radeon_bo_va *bo_va;
|
|
int r = 0;
|
|
|
|
spin_lock(&vm->status_lock);
|
|
while (!list_empty(&vm->freed)) {
|
|
bo_va = list_first_entry(&vm->freed,
|
|
struct radeon_bo_va, vm_status);
|
|
spin_unlock(&vm->status_lock);
|
|
|
|
r = radeon_vm_bo_update(rdev, bo_va, NULL);
|
|
radeon_bo_unref(&bo_va->bo);
|
|
radeon_fence_unref(&bo_va->last_pt_update);
|
|
spin_lock(&vm->status_lock);
|
|
list_del(&bo_va->vm_status);
|
|
kfree(bo_va);
|
|
if (r)
|
|
break;
|
|
|
|
}
|
|
spin_unlock(&vm->status_lock);
|
|
return r;
|
|
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_clear_invalids - clear invalidated BOs in the PT
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @vm: requested vm
|
|
*
|
|
* Make sure all invalidated BOs are cleared in the PT.
|
|
* Returns 0 for success.
|
|
*
|
|
* PTs have to be reserved and mutex must be locked!
|
|
*/
|
|
int radeon_vm_clear_invalids(struct radeon_device *rdev,
|
|
struct radeon_vm *vm)
|
|
{
|
|
struct radeon_bo_va *bo_va;
|
|
int r;
|
|
|
|
spin_lock(&vm->status_lock);
|
|
while (!list_empty(&vm->invalidated)) {
|
|
bo_va = list_first_entry(&vm->invalidated,
|
|
struct radeon_bo_va, vm_status);
|
|
spin_unlock(&vm->status_lock);
|
|
|
|
r = radeon_vm_bo_update(rdev, bo_va, NULL);
|
|
if (r)
|
|
return r;
|
|
|
|
spin_lock(&vm->status_lock);
|
|
}
|
|
spin_unlock(&vm->status_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_bo_rmv - remove a bo to a specific vm
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @bo_va: requested bo_va
|
|
*
|
|
* Remove @bo_va->bo from the requested vm (cayman+).
|
|
*
|
|
* Object have to be reserved!
|
|
*/
|
|
void radeon_vm_bo_rmv(struct radeon_device *rdev,
|
|
struct radeon_bo_va *bo_va)
|
|
{
|
|
struct radeon_vm *vm = bo_va->vm;
|
|
|
|
list_del(&bo_va->bo_list);
|
|
|
|
mutex_lock(&vm->mutex);
|
|
if (bo_va->it.start || bo_va->it.last)
|
|
interval_tree_remove(&bo_va->it, &vm->va);
|
|
|
|
spin_lock(&vm->status_lock);
|
|
list_del(&bo_va->vm_status);
|
|
if (bo_va->it.start || bo_va->it.last) {
|
|
bo_va->bo = radeon_bo_ref(bo_va->bo);
|
|
list_add(&bo_va->vm_status, &vm->freed);
|
|
} else {
|
|
radeon_fence_unref(&bo_va->last_pt_update);
|
|
kfree(bo_va);
|
|
}
|
|
spin_unlock(&vm->status_lock);
|
|
|
|
mutex_unlock(&vm->mutex);
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_bo_invalidate - mark the bo as invalid
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @vm: requested vm
|
|
* @bo: radeon buffer object
|
|
*
|
|
* Mark @bo as invalid (cayman+).
|
|
*/
|
|
void radeon_vm_bo_invalidate(struct radeon_device *rdev,
|
|
struct radeon_bo *bo)
|
|
{
|
|
struct radeon_bo_va *bo_va;
|
|
|
|
list_for_each_entry(bo_va, &bo->va, bo_list) {
|
|
spin_lock(&bo_va->vm->status_lock);
|
|
if (list_empty(&bo_va->vm_status) &&
|
|
(bo_va->it.start || bo_va->it.last))
|
|
list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
|
|
spin_unlock(&bo_va->vm->status_lock);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_init - initialize a vm instance
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @vm: requested vm
|
|
*
|
|
* Init @vm fields (cayman+).
|
|
*/
|
|
int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
|
|
{
|
|
const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE,
|
|
RADEON_VM_PTE_COUNT * 8);
|
|
unsigned pd_size, pd_entries, pts_size;
|
|
int i, r;
|
|
|
|
vm->ib_bo_va = NULL;
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
vm->ids[i].id = 0;
|
|
vm->ids[i].flushed_updates = NULL;
|
|
vm->ids[i].last_id_use = NULL;
|
|
}
|
|
mutex_init(&vm->mutex);
|
|
vm->va = RB_ROOT_CACHED;
|
|
spin_lock_init(&vm->status_lock);
|
|
INIT_LIST_HEAD(&vm->invalidated);
|
|
INIT_LIST_HEAD(&vm->freed);
|
|
INIT_LIST_HEAD(&vm->cleared);
|
|
|
|
pd_size = radeon_vm_directory_size(rdev);
|
|
pd_entries = radeon_vm_num_pdes(rdev);
|
|
|
|
/* allocate page table array */
|
|
pts_size = pd_entries * sizeof(struct radeon_vm_pt);
|
|
vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
|
|
if (vm->page_tables == NULL) {
|
|
DRM_ERROR("Cannot allocate memory for page table array\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
r = radeon_bo_create(rdev, pd_size, align, true,
|
|
RADEON_GEM_DOMAIN_VRAM, 0, NULL,
|
|
NULL, &vm->page_directory);
|
|
if (r)
|
|
return r;
|
|
|
|
r = radeon_vm_clear_bo(rdev, vm->page_directory);
|
|
if (r) {
|
|
radeon_bo_unref(&vm->page_directory);
|
|
vm->page_directory = NULL;
|
|
return r;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* radeon_vm_fini - tear down a vm instance
|
|
*
|
|
* @rdev: radeon_device pointer
|
|
* @vm: requested vm
|
|
*
|
|
* Tear down @vm (cayman+).
|
|
* Unbind the VM and remove all bos from the vm bo list
|
|
*/
|
|
void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
|
|
{
|
|
struct radeon_bo_va *bo_va, *tmp;
|
|
int i, r;
|
|
|
|
if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
|
|
dev_err(rdev->dev, "still active bo inside vm\n");
|
|
}
|
|
rbtree_postorder_for_each_entry_safe(bo_va, tmp,
|
|
&vm->va.rb_root, it.rb) {
|
|
interval_tree_remove(&bo_va->it, &vm->va);
|
|
r = radeon_bo_reserve(bo_va->bo, false);
|
|
if (!r) {
|
|
list_del_init(&bo_va->bo_list);
|
|
radeon_bo_unreserve(bo_va->bo);
|
|
radeon_fence_unref(&bo_va->last_pt_update);
|
|
kfree(bo_va);
|
|
}
|
|
}
|
|
list_for_each_entry_safe(bo_va, tmp, &vm->freed, vm_status) {
|
|
radeon_bo_unref(&bo_va->bo);
|
|
radeon_fence_unref(&bo_va->last_pt_update);
|
|
kfree(bo_va);
|
|
}
|
|
|
|
for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
|
|
radeon_bo_unref(&vm->page_tables[i].bo);
|
|
kfree(vm->page_tables);
|
|
|
|
radeon_bo_unref(&vm->page_directory);
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
radeon_fence_unref(&vm->ids[i].flushed_updates);
|
|
radeon_fence_unref(&vm->ids[i].last_id_use);
|
|
}
|
|
|
|
mutex_destroy(&vm->mutex);
|
|
}
|