![Maxime Ripard](/assets/img/avatar_default.png)
We need to backmerge drm-next to fix the komeda build failure. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
659 lines
16 KiB
C
659 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* rcar_du_kms.c -- R-Car Display Unit Mode Setting
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*
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_device.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_vblank.h>
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#include <linux/of_graph.h>
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#include <linux/wait.h>
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#include "rcar_du_crtc.h"
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#include "rcar_du_drv.h"
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#include "rcar_du_encoder.h"
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#include "rcar_du_kms.h"
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#include "rcar_du_regs.h"
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#include "rcar_du_vsp.h"
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/* -----------------------------------------------------------------------------
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* Format helpers
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*/
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static const struct rcar_du_format_info rcar_du_format_infos[] = {
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{
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.fourcc = DRM_FORMAT_RGB565,
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.bpp = 16,
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.planes = 1,
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.pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
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.edf = PnDDCR4_EDF_NONE,
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}, {
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.fourcc = DRM_FORMAT_ARGB1555,
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.bpp = 16,
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.planes = 1,
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.pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
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.edf = PnDDCR4_EDF_NONE,
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}, {
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.fourcc = DRM_FORMAT_XRGB1555,
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.bpp = 16,
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.planes = 1,
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.pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
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.edf = PnDDCR4_EDF_NONE,
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}, {
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.fourcc = DRM_FORMAT_XRGB8888,
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.bpp = 32,
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.planes = 1,
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.pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
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.edf = PnDDCR4_EDF_RGB888,
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}, {
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.fourcc = DRM_FORMAT_ARGB8888,
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.bpp = 32,
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.planes = 1,
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.pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
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.edf = PnDDCR4_EDF_ARGB8888,
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}, {
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.fourcc = DRM_FORMAT_UYVY,
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.bpp = 16,
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.planes = 1,
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.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
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.edf = PnDDCR4_EDF_NONE,
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}, {
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.fourcc = DRM_FORMAT_YUYV,
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.bpp = 16,
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.planes = 1,
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.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
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.edf = PnDDCR4_EDF_NONE,
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}, {
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.fourcc = DRM_FORMAT_NV12,
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.bpp = 12,
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.planes = 2,
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.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
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.edf = PnDDCR4_EDF_NONE,
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}, {
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.fourcc = DRM_FORMAT_NV21,
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.bpp = 12,
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.planes = 2,
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.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
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.edf = PnDDCR4_EDF_NONE,
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}, {
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.fourcc = DRM_FORMAT_NV16,
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.bpp = 16,
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.planes = 2,
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.pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
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.edf = PnDDCR4_EDF_NONE,
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},
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/*
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* The following formats are not supported on Gen2 and thus have no
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* associated .pnmr or .edf settings.
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*/
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{
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.fourcc = DRM_FORMAT_RGB332,
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.bpp = 8,
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.planes = 1,
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}, {
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.fourcc = DRM_FORMAT_ARGB4444,
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.bpp = 16,
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.planes = 1,
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}, {
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.fourcc = DRM_FORMAT_XRGB4444,
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.bpp = 16,
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.planes = 1,
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}, {
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.fourcc = DRM_FORMAT_BGR888,
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.bpp = 24,
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.planes = 1,
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}, {
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.fourcc = DRM_FORMAT_RGB888,
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.bpp = 24,
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.planes = 1,
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}, {
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.fourcc = DRM_FORMAT_BGRA8888,
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.bpp = 32,
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.planes = 1,
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}, {
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.fourcc = DRM_FORMAT_BGRX8888,
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.bpp = 32,
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.planes = 1,
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}, {
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.fourcc = DRM_FORMAT_YVYU,
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.bpp = 16,
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.planes = 1,
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}, {
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.fourcc = DRM_FORMAT_NV61,
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.bpp = 16,
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.planes = 2,
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}, {
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.fourcc = DRM_FORMAT_YUV420,
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.bpp = 12,
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.planes = 3,
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}, {
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.fourcc = DRM_FORMAT_YVU420,
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.bpp = 12,
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.planes = 3,
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}, {
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.fourcc = DRM_FORMAT_YUV422,
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.bpp = 16,
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.planes = 3,
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}, {
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.fourcc = DRM_FORMAT_YVU422,
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.bpp = 16,
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.planes = 3,
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}, {
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.fourcc = DRM_FORMAT_YUV444,
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.bpp = 24,
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.planes = 3,
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}, {
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.fourcc = DRM_FORMAT_YVU444,
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.bpp = 24,
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.planes = 3,
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},
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};
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const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) {
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if (rcar_du_format_infos[i].fourcc == fourcc)
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return &rcar_du_format_infos[i];
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}
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return NULL;
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}
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/* -----------------------------------------------------------------------------
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* Frame buffer
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*/
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int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
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struct drm_mode_create_dumb *args)
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{
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struct rcar_du_device *rcdu = dev->dev_private;
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unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
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unsigned int align;
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/*
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* The R8A7779 DU requires a 16 pixels pitch alignment as documented,
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* but the R8A7790 DU seems to require a 128 bytes pitch alignment.
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*/
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if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
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align = 128;
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else
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align = 16 * args->bpp / 8;
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args->pitch = roundup(min_pitch, align);
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return drm_gem_cma_dumb_create_internal(file, dev, args);
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}
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static struct drm_framebuffer *
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rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
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const struct drm_mode_fb_cmd2 *mode_cmd)
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{
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struct rcar_du_device *rcdu = dev->dev_private;
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const struct rcar_du_format_info *format;
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unsigned int max_pitch;
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unsigned int align;
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unsigned int i;
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format = rcar_du_format_info(mode_cmd->pixel_format);
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if (format == NULL) {
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dev_dbg(dev->dev, "unsupported pixel format %08x\n",
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mode_cmd->pixel_format);
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return ERR_PTR(-EINVAL);
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}
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if (rcdu->info->gen < 3) {
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/*
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* On Gen2 the DU limits the pitch to 4095 pixels and requires
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* buffers to be aligned to a 16 pixels boundary (or 128 bytes
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* on some platforms).
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*/
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unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
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max_pitch = 4095 * bpp;
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if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
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align = 128;
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else
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align = 16 * bpp;
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} else {
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/*
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* On Gen3 the memory interface is handled by the VSP that
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* limits the pitch to 65535 bytes and has no alignment
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* constraint.
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*/
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max_pitch = 65535;
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align = 1;
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}
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if (mode_cmd->pitches[0] & (align - 1) ||
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mode_cmd->pitches[0] > max_pitch) {
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dev_dbg(dev->dev, "invalid pitch value %u\n",
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mode_cmd->pitches[0]);
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return ERR_PTR(-EINVAL);
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}
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for (i = 1; i < format->planes; ++i) {
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if (mode_cmd->pitches[i] != mode_cmd->pitches[0]) {
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dev_dbg(dev->dev,
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"luma and chroma pitches do not match\n");
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return ERR_PTR(-EINVAL);
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}
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}
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return drm_gem_fb_create(dev, file_priv, mode_cmd);
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}
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/* -----------------------------------------------------------------------------
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* Atomic Check and Update
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*/
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static int rcar_du_atomic_check(struct drm_device *dev,
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struct drm_atomic_state *state)
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{
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struct rcar_du_device *rcdu = dev->dev_private;
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int ret;
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ret = drm_atomic_helper_check(dev, state);
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if (ret)
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return ret;
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if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
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return 0;
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return rcar_du_atomic_check_planes(dev, state);
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}
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static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = old_state->dev;
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struct rcar_du_device *rcdu = dev->dev_private;
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struct drm_crtc_state *crtc_state;
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struct drm_crtc *crtc;
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unsigned int i;
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/*
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* Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
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* when starting the CRTCs.
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*/
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rcdu->dpad1_source = -1;
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for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
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struct rcar_du_crtc_state *rcrtc_state =
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to_rcar_crtc_state(crtc_state);
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
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rcdu->dpad0_source = rcrtc->index;
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if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
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rcdu->dpad1_source = rcrtc->index;
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}
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/* Apply the atomic update. */
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drm_atomic_helper_commit_modeset_disables(dev, old_state);
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drm_atomic_helper_commit_planes(dev, old_state,
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DRM_PLANE_COMMIT_ACTIVE_ONLY);
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drm_atomic_helper_commit_modeset_enables(dev, old_state);
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drm_atomic_helper_commit_hw_done(old_state);
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drm_atomic_helper_wait_for_flip_done(dev, old_state);
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drm_atomic_helper_cleanup_planes(dev, old_state);
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}
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/* -----------------------------------------------------------------------------
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* Initialization
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*/
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static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
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.atomic_commit_tail = rcar_du_atomic_commit_tail,
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};
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static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
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.fb_create = rcar_du_fb_create,
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.atomic_check = rcar_du_atomic_check,
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.atomic_commit = drm_atomic_helper_commit,
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};
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static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
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enum rcar_du_output output,
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struct of_endpoint *ep)
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{
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struct device_node *entity;
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int ret;
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/* Locate the connected entity and initialize the encoder. */
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entity = of_graph_get_remote_port_parent(ep->local_node);
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if (!entity) {
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dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
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ep->local_node);
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return -ENODEV;
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}
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if (!of_device_is_available(entity)) {
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dev_dbg(rcdu->dev,
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"connected entity %pOF is disabled, skipping\n",
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entity);
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of_node_put(entity);
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return -ENODEV;
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}
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ret = rcar_du_encoder_init(rcdu, output, entity);
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if (ret && ret != -EPROBE_DEFER)
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dev_warn(rcdu->dev,
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"failed to initialize encoder %pOF on output %u (%d), skipping\n",
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entity, output, ret);
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of_node_put(entity);
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return ret;
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}
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static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
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{
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struct device_node *np = rcdu->dev->of_node;
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struct device_node *ep_node;
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unsigned int num_encoders = 0;
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/*
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* Iterate over the endpoints and create one encoder for each output
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* pipeline.
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*/
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for_each_endpoint_of_node(np, ep_node) {
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enum rcar_du_output output;
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struct of_endpoint ep;
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unsigned int i;
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int ret;
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ret = of_graph_parse_endpoint(ep_node, &ep);
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if (ret < 0) {
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of_node_put(ep_node);
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return ret;
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}
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/* Find the output route corresponding to the port number. */
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for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
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if (rcdu->info->routes[i].possible_crtcs &&
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rcdu->info->routes[i].port == ep.port) {
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output = i;
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break;
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}
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}
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if (i == RCAR_DU_OUTPUT_MAX) {
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dev_warn(rcdu->dev,
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"port %u references unexisting output, skipping\n",
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ep.port);
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continue;
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}
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/* Process the output pipeline. */
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ret = rcar_du_encoders_init_one(rcdu, output, &ep);
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if (ret < 0) {
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if (ret == -EPROBE_DEFER) {
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of_node_put(ep_node);
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return ret;
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}
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continue;
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}
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num_encoders++;
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}
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return num_encoders;
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}
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static int rcar_du_properties_init(struct rcar_du_device *rcdu)
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{
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/*
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* The color key is expressed as an RGB888 triplet stored in a 32-bit
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* integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
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* or enable source color keying (1).
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*/
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rcdu->props.colorkey =
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drm_property_create_range(rcdu->ddev, 0, "colorkey",
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0, 0x01ffffff);
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if (rcdu->props.colorkey == NULL)
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return -ENOMEM;
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return 0;
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}
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static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
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{
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const struct device_node *np = rcdu->dev->of_node;
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struct of_phandle_args args;
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struct {
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struct device_node *np;
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unsigned int crtcs_mask;
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} vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
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unsigned int vsps_count = 0;
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unsigned int cells;
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unsigned int i;
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int ret;
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/*
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* First parse the DT vsps property to populate the list of VSPs. Each
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* entry contains a pointer to the VSP DT node and a bitmask of the
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* connected DU CRTCs.
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*/
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cells = of_property_count_u32_elems(np, "vsps") / rcdu->num_crtcs - 1;
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if (cells > 1)
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return -EINVAL;
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for (i = 0; i < rcdu->num_crtcs; ++i) {
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unsigned int j;
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ret = of_parse_phandle_with_fixed_args(np, "vsps", cells, i,
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&args);
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if (ret < 0)
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goto error;
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/*
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* Add the VSP to the list or update the corresponding existing
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* entry if the VSP has already been added.
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*/
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for (j = 0; j < vsps_count; ++j) {
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if (vsps[j].np == args.np)
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break;
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}
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if (j < vsps_count)
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of_node_put(args.np);
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else
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vsps[vsps_count++].np = args.np;
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vsps[j].crtcs_mask |= BIT(i);
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/* Store the VSP pointer and pipe index in the CRTC. */
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rcdu->crtcs[i].vsp = &rcdu->vsps[j];
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rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
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}
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/*
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* Then initialize all the VSPs from the node pointers and CRTCs bitmask
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* computed previously.
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*/
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for (i = 0; i < vsps_count; ++i) {
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struct rcar_du_vsp *vsp = &rcdu->vsps[i];
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vsp->index = i;
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vsp->dev = rcdu;
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ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
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if (ret < 0)
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goto error;
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}
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return 0;
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error:
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for (i = 0; i < ARRAY_SIZE(vsps); ++i)
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of_node_put(vsps[i].np);
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return ret;
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}
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int rcar_du_modeset_init(struct rcar_du_device *rcdu)
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{
|
|
static const unsigned int mmio_offsets[] = {
|
|
DU0_REG_OFFSET, DU2_REG_OFFSET
|
|
};
|
|
|
|
struct drm_device *dev = rcdu->ddev;
|
|
struct drm_encoder *encoder;
|
|
unsigned int dpad0_sources;
|
|
unsigned int num_encoders;
|
|
unsigned int num_groups;
|
|
unsigned int swindex;
|
|
unsigned int hwindex;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
drm_mode_config_init(dev);
|
|
|
|
dev->mode_config.min_width = 0;
|
|
dev->mode_config.min_height = 0;
|
|
dev->mode_config.normalize_zpos = true;
|
|
dev->mode_config.funcs = &rcar_du_mode_config_funcs;
|
|
dev->mode_config.helper_private = &rcar_du_mode_config_helper;
|
|
|
|
if (rcdu->info->gen < 3) {
|
|
dev->mode_config.max_width = 4095;
|
|
dev->mode_config.max_height = 2047;
|
|
} else {
|
|
/*
|
|
* The Gen3 DU uses the VSP1 for memory access, and is limited
|
|
* to frame sizes of 8190x8190.
|
|
*/
|
|
dev->mode_config.max_width = 8190;
|
|
dev->mode_config.max_height = 8190;
|
|
}
|
|
|
|
rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
|
|
|
|
ret = rcar_du_properties_init(rcdu);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/*
|
|
* Initialize vertical blanking interrupts handling. Start with vblank
|
|
* disabled for all CRTCs.
|
|
*/
|
|
ret = drm_vblank_init(dev, rcdu->num_crtcs);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Initialize the groups. */
|
|
num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
|
|
|
|
for (i = 0; i < num_groups; ++i) {
|
|
struct rcar_du_group *rgrp = &rcdu->groups[i];
|
|
|
|
mutex_init(&rgrp->lock);
|
|
|
|
rgrp->dev = rcdu;
|
|
rgrp->mmio_offset = mmio_offsets[i];
|
|
rgrp->index = i;
|
|
/* Extract the channel mask for this group only. */
|
|
rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
|
|
& GENMASK(1, 0);
|
|
rgrp->num_crtcs = hweight8(rgrp->channels_mask);
|
|
|
|
/*
|
|
* If we have more than one CRTCs in this group pre-associate
|
|
* the low-order planes with CRTC 0 and the high-order planes
|
|
* with CRTC 1 to minimize flicker occurring when the
|
|
* association is changed.
|
|
*/
|
|
rgrp->dptsr_planes = rgrp->num_crtcs > 1
|
|
? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
|
|
: 0;
|
|
|
|
if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
|
|
ret = rcar_du_planes_init(rgrp);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* Initialize the compositors. */
|
|
if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
|
|
ret = rcar_du_vsps_init(rcdu);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
/* Create the CRTCs. */
|
|
for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
|
|
struct rcar_du_group *rgrp;
|
|
|
|
/* Skip unpopulated DU channels. */
|
|
if (!(rcdu->info->channels_mask & BIT(hwindex)))
|
|
continue;
|
|
|
|
rgrp = &rcdu->groups[hwindex / 2];
|
|
|
|
ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
/* Initialize the encoders. */
|
|
ret = rcar_du_encoders_init(rcdu);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (ret == 0) {
|
|
dev_err(rcdu->dev, "error: no encoder could be initialized\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
num_encoders = ret;
|
|
|
|
/*
|
|
* Set the possible CRTCs and possible clones. There's always at least
|
|
* one way for all encoders to clone each other, set all bits in the
|
|
* possible clones field.
|
|
*/
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
|
struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
|
|
const struct rcar_du_output_routing *route =
|
|
&rcdu->info->routes[renc->output];
|
|
|
|
encoder->possible_crtcs = route->possible_crtcs;
|
|
encoder->possible_clones = (1 << num_encoders) - 1;
|
|
}
|
|
|
|
/*
|
|
* Initialize the default DPAD0 source to the index of the first DU
|
|
* channel that can be connected to DPAD0. The exact value doesn't
|
|
* matter as it should be overwritten by mode setting for the RGB
|
|
* output, but it is nonetheless required to ensure a valid initial
|
|
* hardware configuration on Gen3 where DU0 can't always be connected to
|
|
* DPAD0.
|
|
*/
|
|
dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
|
|
rcdu->dpad0_source = ffs(dpad0_sources) - 1;
|
|
|
|
drm_mode_config_reset(dev);
|
|
|
|
drm_kms_helper_poll_init(dev);
|
|
|
|
return 0;
|
|
}
|