![Laurent Pinchart](/assets/img/avatar_default.png)
On the D3 and E3 platforms, the LVDS internal PLL supplies the pixel clock to the DU. This works automatically for LVDS outputs as the LVDS encoder is enabled through the bridge API, enabling the internal PLL and clock output. However, when using the DU DPAD output with the LVDS outputs turned off, the LVDS PLL needs to be controlled manually. Add an API to do so, to be called by the DU driver. The drivers/gpu/drm/rcar-du/ directory has to be treated as obj-y unconditionally, as the LVDS driver could be built-in while the DU driver is compiled as a module. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
890 lines
23 KiB
C
890 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* rcar_lvds.c -- R-Car LVDS Encoder
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*
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* Copyright (C) 2013-2018 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_probe_helper.h>
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#include "rcar_lvds.h"
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#include "rcar_lvds_regs.h"
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struct rcar_lvds;
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/* Keep in sync with the LVDCR0.LVMD hardware register values. */
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enum rcar_lvds_mode {
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RCAR_LVDS_MODE_JEIDA = 0,
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RCAR_LVDS_MODE_MIRROR = 1,
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RCAR_LVDS_MODE_VESA = 4,
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};
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#define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
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#define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */
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#define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */
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#define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
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#define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
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struct rcar_lvds_device_info {
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unsigned int gen;
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unsigned int quirks;
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void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
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};
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struct rcar_lvds {
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struct device *dev;
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const struct rcar_lvds_device_info *info;
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct drm_connector connector;
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struct drm_panel *panel;
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void __iomem *mmio;
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struct {
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struct clk *mod; /* CPG module clock */
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struct clk *extal; /* External clock */
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struct clk *dotclkin[2]; /* External DU clocks */
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} clocks;
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bool enabled;
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struct drm_display_mode display_mode;
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enum rcar_lvds_mode mode;
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};
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#define bridge_to_rcar_lvds(bridge) \
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container_of(bridge, struct rcar_lvds, bridge)
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#define connector_to_rcar_lvds(connector) \
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container_of(connector, struct rcar_lvds, connector)
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static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
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{
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iowrite32(data, lvds->mmio + reg);
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}
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/* -----------------------------------------------------------------------------
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* Connector & Panel
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*/
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static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
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{
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struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
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return drm_panel_get_modes(lvds->panel);
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}
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static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
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struct drm_connector_state *state)
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{
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struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
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const struct drm_display_mode *panel_mode;
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struct drm_crtc_state *crtc_state;
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if (!state->crtc)
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return 0;
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if (list_empty(&connector->modes)) {
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dev_dbg(lvds->dev, "connector: empty modes list\n");
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return -EINVAL;
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}
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panel_mode = list_first_entry(&connector->modes,
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struct drm_display_mode, head);
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/* We're not allowed to modify the resolution. */
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crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
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crtc_state->mode.vdisplay != panel_mode->vdisplay)
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return -EINVAL;
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/* The flat panel mode is fixed, just copy it to the adjusted mode. */
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drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
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return 0;
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}
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static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
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.get_modes = rcar_lvds_connector_get_modes,
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.atomic_check = rcar_lvds_connector_atomic_check,
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};
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static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
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.reset = drm_atomic_helper_connector_reset,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = drm_connector_cleanup,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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/* -----------------------------------------------------------------------------
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* PLL Setup
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*/
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static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
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{
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u32 val;
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if (freq < 39000000)
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val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
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else if (freq < 61000000)
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val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
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else if (freq < 121000000)
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val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
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else
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val = LVDPLLCR_PLLDLYCNT_150M;
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rcar_lvds_write(lvds, LVDPLLCR, val);
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}
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static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
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{
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u32 val;
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if (freq < 42000000)
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val = LVDPLLCR_PLLDIVCNT_42M;
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else if (freq < 85000000)
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val = LVDPLLCR_PLLDIVCNT_85M;
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else if (freq < 128000000)
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val = LVDPLLCR_PLLDIVCNT_128M;
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else
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val = LVDPLLCR_PLLDIVCNT_148M;
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rcar_lvds_write(lvds, LVDPLLCR, val);
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}
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struct pll_info {
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unsigned long diff;
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unsigned int pll_m;
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unsigned int pll_n;
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unsigned int pll_e;
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unsigned int div;
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u32 clksel;
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};
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static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
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unsigned long target, struct pll_info *pll,
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u32 clksel, bool dot_clock_only)
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{
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unsigned int div7 = dot_clock_only ? 1 : 7;
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unsigned long output;
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unsigned long fin;
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unsigned int m_min;
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unsigned int m_max;
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unsigned int m;
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int error;
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if (!clk)
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return;
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/*
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* The LVDS PLL is made of a pre-divider and a multiplier (strangely
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* enough called M and N respectively), followed by a post-divider E.
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*
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* ,-----. ,-----. ,-----. ,-----.
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* Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
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* `-----' ,-> | | `-----' | `-----'
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* | `-----' |
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* | ,-----. |
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* `-------- | 1/N | <-------'
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* `-----'
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*
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* The clock output by the PLL is then further divided by a programmable
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* divider DIV to achieve the desired target frequency. Finally, an
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* optional fixed /7 divider is used to convert the bit clock to a pixel
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* clock (as LVDS transmits 7 bits per lane per clock sample).
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*
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* ,-------. ,-----. |\
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* Fout --> | 1/DIV | --> | 1/7 | --> | |
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* `-------' | `-----' | | --> dot clock
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* `------------> | |
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* |/
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*
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* The /7 divider is optional, it is enabled when the LVDS PLL is used
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* to drive the LVDS encoder, and disabled when used to generate a dot
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* clock for the DU RGB output, without using the LVDS encoder.
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*
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* The PLL allowed input frequency range is 12 MHz to 192 MHz.
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*/
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fin = clk_get_rate(clk);
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if (fin < 12000000 || fin > 192000000)
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return;
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/*
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* The comparison frequency range is 12 MHz to 24 MHz, which limits the
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* allowed values for the pre-divider M (normal range 1-8).
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*
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* Fpfd = Fin / M
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*/
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m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
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m_max = min_t(unsigned int, 8, fin / 12000000);
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for (m = m_min; m <= m_max; ++m) {
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unsigned long fpfd;
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unsigned int n_min;
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unsigned int n_max;
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unsigned int n;
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/*
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* The VCO operating range is 900 Mhz to 1800 MHz, which limits
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* the allowed values for the multiplier N (normal range
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* 60-120).
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*
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* Fvco = Fin * N / M
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*/
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fpfd = fin / m;
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n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
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n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
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for (n = n_min; n < n_max; ++n) {
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unsigned long fvco;
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unsigned int e_min;
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unsigned int e;
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/*
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* The output frequency is limited to 1039.5 MHz,
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* limiting again the allowed values for the
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* post-divider E (normal value 1, 2 or 4).
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*
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* Fout = Fvco / E
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*/
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fvco = fpfd * n;
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e_min = fvco > 1039500000 ? 1 : 0;
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for (e = e_min; e < 3; ++e) {
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unsigned long fout;
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unsigned long diff;
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unsigned int div;
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/*
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* Finally we have a programable divider after
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* the PLL, followed by a an optional fixed /7
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* divider.
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*/
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fout = fvco / (1 << e) / div7;
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div = DIV_ROUND_CLOSEST(fout, target);
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diff = abs(fout / div - target);
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if (diff < pll->diff) {
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pll->diff = diff;
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pll->pll_m = m;
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pll->pll_n = n;
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pll->pll_e = e;
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pll->div = div;
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pll->clksel = clksel;
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if (diff == 0)
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goto done;
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}
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}
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}
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}
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done:
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output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
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/ div7 / pll->div;
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error = (long)(output - target) * 10000 / (long)target;
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dev_dbg(lvds->dev,
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"%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
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clk, fin, output, target, error / 100,
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error < 0 ? -error % 100 : error % 100,
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pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
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}
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static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
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unsigned int freq, bool dot_clock_only)
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{
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struct pll_info pll = { .diff = (unsigned long)-1 };
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u32 lvdpllcr;
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rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
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LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
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rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
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LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
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rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
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LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
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lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
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| LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
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if (pll.pll_e > 0)
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lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
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| LVDPLLCR_PLLE(pll.pll_e - 1);
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if (dot_clock_only)
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lvdpllcr |= LVDPLLCR_OCKSEL;
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rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
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if (pll.div > 1)
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/*
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* The DIVRESET bit is a misnomer, setting it to 1 deasserts the
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* divisor reset.
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*/
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rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
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LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
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else
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rcar_lvds_write(lvds, LVDDIV, 0);
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}
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static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
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{
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__rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
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}
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/* -----------------------------------------------------------------------------
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* Clock - D3/E3 only
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*/
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int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
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{
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struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
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int ret;
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if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
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return -ENODEV;
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dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
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WARN_ON(lvds->enabled);
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ret = clk_prepare_enable(lvds->clocks.mod);
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if (ret < 0)
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return ret;
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__rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
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lvds->enabled = true;
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return 0;
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}
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EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
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void rcar_lvds_clk_disable(struct drm_bridge *bridge)
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{
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struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
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if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
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return;
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dev_dbg(lvds->dev, "disabling LVDS PLL\n");
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WARN_ON(!lvds->enabled);
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rcar_lvds_write(lvds, LVDPLLCR, 0);
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clk_disable_unprepare(lvds->clocks.mod);
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lvds->enabled = false;
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}
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EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
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/* -----------------------------------------------------------------------------
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* Bridge
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*/
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static void rcar_lvds_enable(struct drm_bridge *bridge)
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{
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struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
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const struct drm_display_mode *mode = &lvds->display_mode;
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/*
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* FIXME: We should really retrieve the CRTC through the state, but how
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* do we get a state pointer?
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*/
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struct drm_crtc *crtc = lvds->bridge.encoder->crtc;
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u32 lvdhcr;
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u32 lvdcr0;
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int ret;
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WARN_ON(lvds->enabled);
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ret = clk_prepare_enable(lvds->clocks.mod);
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if (ret < 0)
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return;
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/*
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* Hardcode the channels and control signals routing for now.
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*
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* HSYNC -> CTRL0
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* VSYNC -> CTRL1
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* DISP -> CTRL2
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* 0 -> CTRL3
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*/
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rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
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LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
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LVDCTRCR_CTR0SEL_HSYNC);
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if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
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lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
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| LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
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else
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lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
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| LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
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rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
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if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
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/* Disable dual-link mode. */
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rcar_lvds_write(lvds, LVDSTRIPE, 0);
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}
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/* PLL clock configuration. */
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lvds->info->pll_setup(lvds, mode->clock * 1000);
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/* Set the LVDS mode and select the input. */
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lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
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if (drm_crtc_index(crtc) == 2)
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lvdcr0 |= LVDCR0_DUSEL;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1,
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LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
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LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
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if (lvds->info->gen < 3) {
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/* Enable LVDS operation and turn the bias circuitry on. */
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lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
|
|
rcar_lvds_write(lvds, LVDCR0, lvdcr0);
|
|
}
|
|
|
|
if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
|
|
/*
|
|
* Turn the PLL on (simple PLL only, extended PLL is fully
|
|
* controlled through LVDPLLCR).
|
|
*/
|
|
lvdcr0 |= LVDCR0_PLLON;
|
|
rcar_lvds_write(lvds, LVDCR0, lvdcr0);
|
|
}
|
|
|
|
if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
|
|
/* Set LVDS normal mode. */
|
|
lvdcr0 |= LVDCR0_PWD;
|
|
rcar_lvds_write(lvds, LVDCR0, lvdcr0);
|
|
}
|
|
|
|
if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
|
|
/* Turn on the LVDS PHY. */
|
|
lvdcr0 |= LVDCR0_LVEN;
|
|
rcar_lvds_write(lvds, LVDCR0, lvdcr0);
|
|
}
|
|
|
|
if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
|
|
/* Wait for the PLL startup delay (simple PLL only). */
|
|
usleep_range(100, 150);
|
|
}
|
|
|
|
/* Turn the output on. */
|
|
lvdcr0 |= LVDCR0_LVRES;
|
|
rcar_lvds_write(lvds, LVDCR0, lvdcr0);
|
|
|
|
if (lvds->panel) {
|
|
drm_panel_prepare(lvds->panel);
|
|
drm_panel_enable(lvds->panel);
|
|
}
|
|
|
|
lvds->enabled = true;
|
|
}
|
|
|
|
static void rcar_lvds_disable(struct drm_bridge *bridge)
|
|
{
|
|
struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
|
|
|
|
WARN_ON(!lvds->enabled);
|
|
|
|
if (lvds->panel) {
|
|
drm_panel_disable(lvds->panel);
|
|
drm_panel_unprepare(lvds->panel);
|
|
}
|
|
|
|
rcar_lvds_write(lvds, LVDCR0, 0);
|
|
rcar_lvds_write(lvds, LVDCR1, 0);
|
|
rcar_lvds_write(lvds, LVDPLLCR, 0);
|
|
|
|
clk_disable_unprepare(lvds->clocks.mod);
|
|
|
|
lvds->enabled = false;
|
|
}
|
|
|
|
static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
|
|
const struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
/*
|
|
* The internal LVDS encoder has a restricted clock frequency operating
|
|
* range (31MHz to 148.5MHz). Clamp the clock accordingly.
|
|
*/
|
|
adjusted_mode->clock = clamp(adjusted_mode->clock, 31000, 148500);
|
|
|
|
return true;
|
|
}
|
|
|
|
static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
|
|
{
|
|
struct drm_display_info *info = &lvds->connector.display_info;
|
|
enum rcar_lvds_mode mode;
|
|
|
|
/*
|
|
* There is no API yet to retrieve LVDS mode from a bridge, only panels
|
|
* are supported.
|
|
*/
|
|
if (!lvds->panel)
|
|
return;
|
|
|
|
if (!info->num_bus_formats || !info->bus_formats) {
|
|
dev_err(lvds->dev, "no LVDS bus format reported\n");
|
|
return;
|
|
}
|
|
|
|
switch (info->bus_formats[0]) {
|
|
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
|
|
case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
|
|
mode = RCAR_LVDS_MODE_JEIDA;
|
|
break;
|
|
case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
|
|
mode = RCAR_LVDS_MODE_VESA;
|
|
break;
|
|
default:
|
|
dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
|
|
info->bus_formats[0]);
|
|
return;
|
|
}
|
|
|
|
if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
|
|
mode |= RCAR_LVDS_MODE_MIRROR;
|
|
|
|
lvds->mode = mode;
|
|
}
|
|
|
|
static void rcar_lvds_mode_set(struct drm_bridge *bridge,
|
|
const struct drm_display_mode *mode,
|
|
const struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
|
|
|
|
WARN_ON(lvds->enabled);
|
|
|
|
lvds->display_mode = *adjusted_mode;
|
|
|
|
rcar_lvds_get_lvds_mode(lvds);
|
|
}
|
|
|
|
static int rcar_lvds_attach(struct drm_bridge *bridge)
|
|
{
|
|
struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
|
|
struct drm_connector *connector = &lvds->connector;
|
|
struct drm_encoder *encoder = bridge->encoder;
|
|
int ret;
|
|
|
|
/* If we have a next bridge just attach it. */
|
|
if (lvds->next_bridge)
|
|
return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
|
|
bridge);
|
|
|
|
/* Otherwise if we have a panel, create a connector. */
|
|
if (!lvds->panel)
|
|
return 0;
|
|
|
|
ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
|
|
DRM_MODE_CONNECTOR_LVDS);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
|
|
|
|
ret = drm_connector_attach_encoder(connector, encoder);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return drm_panel_attach(lvds->panel, connector);
|
|
}
|
|
|
|
static void rcar_lvds_detach(struct drm_bridge *bridge)
|
|
{
|
|
struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
|
|
|
|
if (lvds->panel)
|
|
drm_panel_detach(lvds->panel);
|
|
}
|
|
|
|
static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
|
|
.attach = rcar_lvds_attach,
|
|
.detach = rcar_lvds_detach,
|
|
.enable = rcar_lvds_enable,
|
|
.disable = rcar_lvds_disable,
|
|
.mode_fixup = rcar_lvds_mode_fixup,
|
|
.mode_set = rcar_lvds_mode_set,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Probe & Remove
|
|
*/
|
|
|
|
static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
|
|
{
|
|
struct device_node *local_output = NULL;
|
|
struct device_node *remote_input = NULL;
|
|
struct device_node *remote = NULL;
|
|
struct device_node *node;
|
|
bool is_bridge = false;
|
|
int ret = 0;
|
|
|
|
local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
|
|
if (!local_output) {
|
|
dev_dbg(lvds->dev, "unconnected port@1\n");
|
|
ret = -ENODEV;
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* Locate the connected entity and infer its type from the number of
|
|
* endpoints.
|
|
*/
|
|
remote = of_graph_get_remote_port_parent(local_output);
|
|
if (!remote) {
|
|
dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
|
|
ret = -ENODEV;
|
|
goto done;
|
|
}
|
|
|
|
if (!of_device_is_available(remote)) {
|
|
dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
|
|
remote);
|
|
ret = -ENODEV;
|
|
goto done;
|
|
}
|
|
|
|
remote_input = of_graph_get_remote_endpoint(local_output);
|
|
|
|
for_each_endpoint_of_node(remote, node) {
|
|
if (node != remote_input) {
|
|
/*
|
|
* We've found one endpoint other than the input, this
|
|
* must be a bridge.
|
|
*/
|
|
is_bridge = true;
|
|
of_node_put(node);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (is_bridge) {
|
|
lvds->next_bridge = of_drm_find_bridge(remote);
|
|
if (!lvds->next_bridge)
|
|
ret = -EPROBE_DEFER;
|
|
} else {
|
|
lvds->panel = of_drm_find_panel(remote);
|
|
if (IS_ERR(lvds->panel))
|
|
ret = PTR_ERR(lvds->panel);
|
|
}
|
|
|
|
done:
|
|
of_node_put(local_output);
|
|
of_node_put(remote_input);
|
|
of_node_put(remote);
|
|
|
|
/*
|
|
* On D3/E3 the LVDS encoder provides a clock to the DU, which can be
|
|
* used for the DPAD output even when the LVDS output is not connected.
|
|
* Don't fail probe in that case as the DU will need the bridge to
|
|
* control the clock.
|
|
*/
|
|
if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
|
|
return ret == -ENODEV ? 0 : ret;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
|
|
bool optional)
|
|
{
|
|
struct clk *clk;
|
|
|
|
clk = devm_clk_get(lvds->dev, name);
|
|
if (!IS_ERR(clk))
|
|
return clk;
|
|
|
|
if (PTR_ERR(clk) == -ENOENT && optional)
|
|
return NULL;
|
|
|
|
if (PTR_ERR(clk) != -EPROBE_DEFER)
|
|
dev_err(lvds->dev, "failed to get %s clock\n",
|
|
name ? name : "module");
|
|
|
|
return clk;
|
|
}
|
|
|
|
static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
|
|
{
|
|
lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
|
|
if (IS_ERR(lvds->clocks.mod))
|
|
return PTR_ERR(lvds->clocks.mod);
|
|
|
|
/*
|
|
* LVDS encoders without an extended PLL have no external clock inputs.
|
|
*/
|
|
if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
|
|
return 0;
|
|
|
|
lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
|
|
if (IS_ERR(lvds->clocks.extal))
|
|
return PTR_ERR(lvds->clocks.extal);
|
|
|
|
lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
|
|
if (IS_ERR(lvds->clocks.dotclkin[0]))
|
|
return PTR_ERR(lvds->clocks.dotclkin[0]);
|
|
|
|
lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
|
|
if (IS_ERR(lvds->clocks.dotclkin[1]))
|
|
return PTR_ERR(lvds->clocks.dotclkin[1]);
|
|
|
|
/* At least one input to the PLL must be available. */
|
|
if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
|
|
!lvds->clocks.dotclkin[1]) {
|
|
dev_err(lvds->dev,
|
|
"no input clock (extal, dclkin.0 or dclkin.1)\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rcar_lvds_probe(struct platform_device *pdev)
|
|
{
|
|
struct rcar_lvds *lvds;
|
|
struct resource *mem;
|
|
int ret;
|
|
|
|
lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
|
|
if (lvds == NULL)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, lvds);
|
|
|
|
lvds->dev = &pdev->dev;
|
|
lvds->info = of_device_get_match_data(&pdev->dev);
|
|
lvds->enabled = false;
|
|
|
|
ret = rcar_lvds_parse_dt(lvds);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
lvds->bridge.driver_private = lvds;
|
|
lvds->bridge.funcs = &rcar_lvds_bridge_ops;
|
|
lvds->bridge.of_node = pdev->dev.of_node;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
|
|
if (IS_ERR(lvds->mmio))
|
|
return PTR_ERR(lvds->mmio);
|
|
|
|
ret = rcar_lvds_get_clocks(lvds);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
drm_bridge_add(&lvds->bridge);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rcar_lvds_remove(struct platform_device *pdev)
|
|
{
|
|
struct rcar_lvds *lvds = platform_get_drvdata(pdev);
|
|
|
|
drm_bridge_remove(&lvds->bridge);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
|
|
.gen = 2,
|
|
.pll_setup = rcar_lvds_pll_setup_gen2,
|
|
};
|
|
|
|
static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
|
|
.gen = 2,
|
|
.quirks = RCAR_LVDS_QUIRK_LANES,
|
|
.pll_setup = rcar_lvds_pll_setup_gen2,
|
|
};
|
|
|
|
static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
|
|
.gen = 3,
|
|
.quirks = RCAR_LVDS_QUIRK_PWD,
|
|
.pll_setup = rcar_lvds_pll_setup_gen3,
|
|
};
|
|
|
|
static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
|
|
.gen = 3,
|
|
.quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
|
|
.pll_setup = rcar_lvds_pll_setup_gen2,
|
|
};
|
|
|
|
static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
|
|
.gen = 3,
|
|
.quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
|
|
| RCAR_LVDS_QUIRK_DUAL_LINK,
|
|
.pll_setup = rcar_lvds_pll_setup_d3_e3,
|
|
};
|
|
|
|
static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
|
|
.gen = 3,
|
|
.quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
|
|
| RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
|
|
.pll_setup = rcar_lvds_pll_setup_d3_e3,
|
|
};
|
|
|
|
static const struct of_device_id rcar_lvds_of_table[] = {
|
|
{ .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
|
|
{ .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
|
|
{ .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
|
|
{ .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
|
|
{ .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
|
|
{ .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
|
|
{ .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
|
|
{ .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
|
|
{ .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
|
|
{ .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
|
|
{ .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
|
|
{ .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
|
|
{ .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
|
|
|
|
static struct platform_driver rcar_lvds_platform_driver = {
|
|
.probe = rcar_lvds_probe,
|
|
.remove = rcar_lvds_remove,
|
|
.driver = {
|
|
.name = "rcar-lvds",
|
|
.of_match_table = rcar_lvds_of_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(rcar_lvds_platform_driver);
|
|
|
|
MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
|
|
MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
|
|
MODULE_LICENSE("GPL");
|