![Jernej Skrabec](/assets/img/avatar_default.png)
Display Engine 3 is an upgrade of DE2 with new features like support for 10 bit color formats and support for AFBC. Most of DE2 code works with DE3, except some small details. Implement basic support for DE3. Support for 10 bit colort formats and AFBC, among others missing features, will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/260238/
177 lines
4.5 KiB
C
177 lines
4.5 KiB
C
/*
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* Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <drm/drmP.h>
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#include "sun8i_csc.h"
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#include "sun8i_mixer.h"
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static const u32 ccsc_base[2][2] = {
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{CCSC00_OFFSET, CCSC01_OFFSET},
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{CCSC10_OFFSET, CCSC11_OFFSET},
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};
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/*
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* Factors are in two's complement format, 10 bits for fractinal part.
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* First tree values in each line are multiplication factor and last
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* value is constant, which is added at the end.
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*/
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static const u32 yuv2rgb[] = {
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0x000004A8, 0x00000000, 0x00000662, 0xFFFC845A,
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0x000004A8, 0xFFFFFE6F, 0xFFFFFCBF, 0x00021DF4,
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0x000004A8, 0x00000813, 0x00000000, 0xFFFBAC4A,
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};
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static const u32 yvu2rgb[] = {
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0x000004A8, 0x00000662, 0x00000000, 0xFFFC845A,
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0x000004A8, 0xFFFFFCBF, 0xFFFFFE6F, 0x00021DF4,
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0x000004A8, 0x00000000, 0x00000813, 0xFFFBAC4A,
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};
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/*
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* DE3 has a bit different CSC units. Factors are in two's complement format.
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* First three factors in a row are multiplication factors which have 17 bits
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* for fractional part. Fourth value in a row is comprised of two factors.
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* Upper 16 bits represents difference, which is subtracted from the input
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* value before multiplication and lower 16 bits represents constant, which
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* is addes at the end.
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*
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* x' = c00 * (x + d0) + c01 * (y + d1) + c02 * (z + d2) + const0
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* y' = c10 * (x + d0) + c11 * (y + d1) + c12 * (z + d2) + const1
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* z' = c20 * (x + d0) + c21 * (y + d1) + c22 * (z + d2) + const2
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*
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* Please note that above formula is true only for Blender CSC. Other DE3 CSC
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* units takes only positive value for difference. From what can be deducted
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* from BSP driver code, those units probably automatically assume that
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* difference has to be subtracted.
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*
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* Layout of factors in table:
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* c00 c01 c02 [d0 const0]
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* c10 c11 c12 [d1 const1]
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* c20 c21 c22 [d2 const2]
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*/
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static const u32 yuv2rgb_de3[] = {
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0x0002542a, 0x00000000, 0x0003312a, 0xffc00000,
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0x0002542a, 0xffff376b, 0xfffe5fc3, 0xfe000000,
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0x0002542a, 0x000408d3, 0x00000000, 0xfe000000,
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};
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static const u32 yvu2rgb_de3[] = {
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0x0002542a, 0x0003312a, 0x00000000, 0xffc00000,
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0x0002542a, 0xfffe5fc3, 0xffff376b, 0xfe000000,
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0x0002542a, 0x00000000, 0x000408d3, 0xfe000000,
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};
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static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
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enum sun8i_csc_mode mode)
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{
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const u32 *table;
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int i, data;
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switch (mode) {
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case SUN8I_CSC_MODE_YUV2RGB:
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table = yuv2rgb;
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break;
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case SUN8I_CSC_MODE_YVU2RGB:
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table = yvu2rgb;
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break;
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default:
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DRM_WARN("Wrong CSC mode specified.\n");
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return;
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}
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for (i = 0; i < 12; i++) {
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data = table[i];
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/* For some reason, 0x200 must be added to constant parts */
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if (((i + 1) & 3) == 0)
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data += 0x200;
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regmap_write(map, SUN8I_CSC_COEFF(base, i), data);
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}
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}
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static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
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enum sun8i_csc_mode mode)
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{
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const u32 *table;
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u32 base_reg;
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switch (mode) {
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case SUN8I_CSC_MODE_YUV2RGB:
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table = yuv2rgb_de3;
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break;
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case SUN8I_CSC_MODE_YVU2RGB:
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table = yvu2rgb_de3;
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break;
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default:
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DRM_WARN("Wrong CSC mode specified.\n");
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return;
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}
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base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0, 0);
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regmap_bulk_write(map, base_reg, table, 12);
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}
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static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable)
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{
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u32 val;
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if (enable)
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val = SUN8I_CSC_CTRL_EN;
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else
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val = 0;
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regmap_update_bits(map, SUN8I_CSC_CTRL(base), SUN8I_CSC_CTRL_EN, val);
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}
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static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable)
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{
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u32 val, mask;
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mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer);
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if (enable)
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val = mask;
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else
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val = 0;
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regmap_update_bits(map, SUN50I_MIXER_BLEND_CSC_CTL(DE3_BLD_BASE),
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mask, val);
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}
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void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
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enum sun8i_csc_mode mode)
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{
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u32 base;
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if (mixer->cfg->is_de3) {
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sun8i_de3_ccsc_set_coefficients(mixer->engine.regs,
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layer, mode);
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return;
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}
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base = ccsc_base[mixer->cfg->ccsc][layer];
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sun8i_csc_set_coefficients(mixer->engine.regs, base, mode);
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}
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void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
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{
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u32 base;
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if (mixer->cfg->is_de3) {
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sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable);
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return;
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}
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base = ccsc_base[mixer->cfg->ccsc][layer];
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sun8i_csc_enable(mixer->engine.regs, base, enable);
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}
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