387720c938
Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
115 lines
2.5 KiB
Plaintext
115 lines
2.5 KiB
Plaintext
/*
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/* First 4KB has pen for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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/ {
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model = "Calxeda ECX-2000";
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compatible = "calxeda,ecx-2000";
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#address-cells = <2>;
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#size-cells = <2>;
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clock-ranges;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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};
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memory@0 {
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name = "memory";
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
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};
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memory@200000000 {
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name = "memory";
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device_type = "memory";
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reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
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};
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soc {
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ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
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timer {
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compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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memory-controller@fff00000 {
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compatible = "calxeda,ecx-2000-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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#address-cells = <1>;
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interrupt-controller;
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interrupts = <1 9 0xf04>;
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reg = <0xfff11000 0x1000>,
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<0xfff12000 0x2000>,
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<0xfff14000 0x2000>,
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<0xfff16000 0x2000>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
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};
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};
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};
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/include/ "ecx-common.dtsi"
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