3590312f47
UART modules can use DMA for offloading data transfers and reducing interrupts, so enable this feature for Exynos5 boards. Tested on Google ChromeBook Snow (Exynos5250), Odroid XU (Exynos5410) and Odroid XU3 (Exynos5422) boards. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
432 lines
9.9 KiB
Plaintext
432 lines
9.9 KiB
Plaintext
/*
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* SAMSUNG EXYNOS5410 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
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* EXYNOS5410 based board files can include this file and provide
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* values for board specfic bindings.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos54xx.dtsi"
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#include "exynos-syscon-restart.dtsi"
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#include <dt-bindings/clock/exynos5410.h>
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#include <dt-bindings/clock/exynos-audss-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "samsung,exynos5410", "samsung,exynos5";
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1600000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1600000000>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1600000000>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1600000000>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pmu_system_controller: system-controller@10040000 {
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compatible = "samsung,exynos5410-pmu", "syscon";
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reg = <0x10040000 0x5000>;
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clock-names = "clkout16";
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clocks = <&fin_pll>;
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#clock-cells = <1>;
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5410-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5410-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
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clock-names = "pll_ref", "pll_in";
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};
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tmu_cpu0: tmu@10060000 {
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compatible = "samsung,exynos5420-tmu";
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reg = <0x10060000 0x100>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_TMU>;
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clock-names = "tmu_apbif";
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#include "exynos4412-tmu-sensor-conf.dtsi"
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};
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tmu_cpu1: tmu@10064000 {
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compatible = "samsung,exynos5420-tmu";
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reg = <0x10064000 0x100>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_TMU>;
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clock-names = "tmu_apbif";
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#include "exynos4412-tmu-sensor-conf.dtsi"
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};
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tmu_cpu2: tmu@10068000 {
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compatible = "samsung,exynos5420-tmu";
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reg = <0x10068000 0x100>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_TMU>;
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clock-names = "tmu_apbif";
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#include "exynos4412-tmu-sensor-conf.dtsi"
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};
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tmu_cpu3: tmu@1006c000 {
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compatible = "samsung,exynos5420-tmu";
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reg = <0x1006c000 0x100>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_TMU>;
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clock-names = "tmu_apbif";
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#include "exynos4412-tmu-sensor-conf.dtsi"
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};
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mmc_0: mmc@12200000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12200000 0x1000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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status = "disabled";
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};
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mmc_1: mmc@12210000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12210000 0x1000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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status = "disabled";
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};
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mmc_2: mmc@12220000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12220000 0x1000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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status = "disabled";
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};
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pinctrl_0: pinctrl@13400000 {
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compatible = "samsung,exynos5410-pinctrl";
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reg = <0x13400000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl_1: pinctrl@14000000 {
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compatible = "samsung,exynos5410-pinctrl";
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reg = <0x14000000 0x1000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_2: pinctrl@10d10000 {
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compatible = "samsung,exynos5410-pinctrl";
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reg = <0x10d10000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_3: pinctrl@03860000 {
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compatible = "samsung,exynos5410-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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pdma0: pdma@12680000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121A0000 0x1000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_PDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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pdma1: pdma@12690000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121B0000 0x1000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_PDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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};
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audi2s0: i2s@03830000 {
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compatible = "samsung,exynos5420-i2s";
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reg = <0x03830000 0x100>;
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dmas = <&pdma0 10
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&pdma0 9
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&pdma0 8>;
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dma-names = "tx", "rx", "tx-sec";
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clocks = <&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_SCLK_I2S>;
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clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk0";
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#sound-dai-cells = <1>;
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samsung,idma-addr = <0x03000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&audi2s0_bus>;
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status = "disabled";
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};
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};
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thermal-zones {
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cpu0_thermal: cpu0-thermal {
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thermal-sensors = <&tmu_cpu0>;
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#include "exynos5420-trip-points.dtsi"
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};
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cpu1_thermal: cpu1-thermal {
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thermal-sensors = <&tmu_cpu1>;
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#include "exynos5420-trip-points.dtsi"
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};
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cpu2_thermal: cpu2-thermal {
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thermal-sensors = <&tmu_cpu2>;
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#include "exynos5420-trip-points.dtsi"
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};
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cpu3_thermal: cpu3-thermal {
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thermal-sensors = <&tmu_cpu3>;
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#include "exynos5420-trip-points.dtsi"
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};
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};
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};
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&i2c_0 {
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clocks = <&clock CLK_I2C0>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_bus>;
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};
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&i2c_1 {
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clocks = <&clock CLK_I2C1>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_bus>;
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};
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&i2c_2 {
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clocks = <&clock CLK_I2C2>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_bus>;
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};
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&i2c_3 {
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clocks = <&clock CLK_I2C3>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_bus>;
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};
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&hsi2c_4 {
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clocks = <&clock CLK_USI0>;
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clock-names = "hsi2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_hs_bus>;
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};
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&hsi2c_5 {
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clocks = <&clock CLK_USI1>;
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clock-names = "hsi2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_hs_bus>;
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};
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&hsi2c_6 {
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clocks = <&clock CLK_USI2>;
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clock-names = "hsi2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_hs_bus>;
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};
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&hsi2c_7 {
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clocks = <&clock CLK_USI3>;
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clock-names = "hsi2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7_hs_bus>;
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};
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&mct {
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clocks = <&fin_pll>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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};
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&pwm {
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clocks = <&clock CLK_PWM>;
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clock-names = "timers";
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};
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&rtc {
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clocks = <&clock CLK_RTC>;
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clock-names = "rtc";
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interrupt-parent = <&pmu_system_controller>;
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status = "disabled";
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};
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&serial_0 {
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clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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dmas = <&pdma0 13>, <&pdma0 14>;
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dma-names = "rx", "tx";
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};
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&serial_1 {
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clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
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clock-names = "uart", "clk_uart_baud0";
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dmas = <&pdma1 15>, <&pdma1 16>;
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dma-names = "rx", "tx";
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};
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&serial_2 {
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clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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dmas = <&pdma0 15>, <&pdma0 16>;
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dma-names = "rx", "tx";
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};
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&serial_3 {
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clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
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clock-names = "uart", "clk_uart_baud0";
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dmas = <&pdma1 17>, <&pdma1 18>;
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dma-names = "rx", "tx";
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};
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&sss {
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clocks = <&clock CLK_SSS>;
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clock-names = "secss";
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};
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&sromc {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x04000000 0x20000
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1 0 0x05000000 0x20000
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2 0 0x06000000 0x20000
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3 0 0x07000000 0x20000>;
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};
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&usbdrd3_0 {
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clocks = <&clock CLK_USBD300>;
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clock-names = "usbdrd30";
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};
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&usbdrd_phy0 {
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clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
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clock-names = "phy", "ref";
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samsung,pmu-syscon = <&pmu_system_controller>;
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};
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&usbdrd3_1 {
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clocks = <&clock CLK_USBD301>;
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clock-names = "usbdrd30";
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};
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&usbdrd_dwc3_1 {
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interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usbdrd_phy1 {
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clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
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clock-names = "phy", "ref";
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samsung,pmu-syscon = <&pmu_system_controller>;
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};
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&usbhost1 {
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clocks = <&clock CLK_USBH20>;
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clock-names = "usbhost";
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};
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&usbhost2 {
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clocks = <&clock CLK_USBH20>;
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clock-names = "usbhost";
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};
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&usb2_phy {
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clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
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clock-names = "phy", "ref";
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samsung,sysreg-phandle = <&sysreg_system_controller>;
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samsung,pmureg-phandle = <&pmu_system_controller>;
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};
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&watchdog {
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clocks = <&clock CLK_WDT>;
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clock-names = "watchdog";
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samsung,syscon-phandle = <&pmu_system_controller>;
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};
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#include "exynos5410-pinctrl.dtsi"
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