e3aeca1d74
The Cortina Gemini has an internal PCI root bus, add this to the device tree, and add interrupt mapping (swizzling) to the relevant systems device trees. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Feng-Hsin Chiang <john453@faraday-tech.com> Cc: Greentime Hu <green.hu@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
157 lines
3.8 KiB
Plaintext
157 lines
3.8 KiB
Plaintext
/*
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* Device Tree file for Cortina systems Gemini SoC
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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interrupt-parent = <&intcon>;
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flash@30000000 {
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compatible = "cortina,gemini-flash", "cfi-flash";
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syscon = <&syscon>;
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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syscon: syscon@40000000 {
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compatible = "cortina,gemini-syscon", "syscon", "simple-mfd";
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reg = <0x40000000 0x1000>;
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&syscon>;
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/* GLOBAL_RESET register */
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offset = <0x0c>;
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/* RESET_GLOBAL | RESET_CPU1 */
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mask = <0xC0000000>;
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};
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};
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watchdog@41000000 {
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compatible = "cortina,gemini-watchdog";
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reg = <0x41000000 0x1000>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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};
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uart0: serial@42000000 {
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compatible = "ns16550a";
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reg = <0x42000000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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};
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timer@43000000 {
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compatible = "cortina,gemini-timer";
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reg = <0x43000000 0x1000>;
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interrupt-parent = <&intcon>;
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interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
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<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
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<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
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syscon = <&syscon>;
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};
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rtc@45000000 {
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compatible = "cortina,gemini-rtc";
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reg = <0x45000000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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};
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intcon: interrupt-controller@48000000 {
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compatible = "faraday,ftintc010";
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reg = <0x48000000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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power-controller@4b000000 {
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compatible = "cortina,gemini-power-controller";
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reg = <0x4b000000 0x100>;
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interrupts = <26 IRQ_TYPE_EDGE_RISING>;
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};
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gpio0: gpio@4d000000 {
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4d000000 0x100>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@4e000000 {
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4e000000 0x100>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@4f000000 {
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4f000000 0x100>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pci@50000000 {
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compatible = "cortina,gemini-pci", "faraday,ftpci100";
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/*
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* The first 256 bytes in the IO range is actually used
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* to configure the host bridge.
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*/
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reg = <0x50000000 0x100>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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status = "disabled";
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bus-range = <0x00 0xff>;
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/* PCI ranges mappings */
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ranges =
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/* 1MiB I/O space 0x50000000-0x500fffff */
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<0x01000000 0 0 0x50000000 0 0x00100000>,
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/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
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<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
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/* DMA ranges */
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dma-ranges =
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/* 128MiB at 0x00000000-0x07ffffff */
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<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
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/* 64MiB at 0x00000000-0x03ffffff */
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<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
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/* 64MiB at 0x00000000-0x03ffffff */
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<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
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/*
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* This PCI host bridge variant has a cascaded interrupt
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* controller embedded in the host bridge.
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*/
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pci_intc: interrupt-controller {
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interrupt-parent = <&intcon>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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};
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