20f12758c9
Commit0976c946a6"arm/versatile: Fix versatile irq specifications" has an off-by-one error on the Versatile AB that has been regressing the Versatile AB hardware for some time. However it seems like the interrupt assignments have never been correct and I have now adjusted them according to the specification. The masks for the valid interrupts made it impossible to assign the right SIC interrupt for the MMCI, so I went in and fixed these to correspond to the specifications, and added references if anyone wants to double-check. Due to the Versatile PB including the Versatile AB as a base DTS file, we need to override and correct some values to correspond to the actual changes in the hardware. For the Versatile PB I don't think the IRQ line assignment for MMCI has ever been correct for either of the two MMCI blocks. It would be nice if someone with the physical PB board could test this. Patch tested on the Versatile AB, QEMU for Versatile AB and QEMU for Versatile PB. Cc: Rob Herring <robh@kernel.org> Cc: Grant Likely <grant.likely@linaro.org> Cc: stable@vger.kernel.org Fixes:0976c946a6("arm/versatile: Fix versatile irq specifications") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
114 lines
2.7 KiB
Plaintext
114 lines
2.7 KiB
Plaintext
#include <versatile-ab.dts>
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/ {
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model = "ARM Versatile PB";
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compatible = "arm,versatile-pb";
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amba {
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/* The Versatile PB is using more SIC IRQ lines than the AB */
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sic: intc@10003000 {
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clear-mask = <0xffffffff>;
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/*
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* Valid interrupt lines mask according to
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* figure 3-30 page 3-74 of ARM DUI 0224B
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*/
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valid-mask = <0x7fe003ff>;
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};
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gpio2: gpio@101e6000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x101e6000 0x1000>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpio3: gpio@101e7000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x101e7000 0x1000>;
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interrupts = <9>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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pci-controller@10001000 {
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compatible = "arm,versatile-pci";
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device_type = "pci";
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reg = <0x10001000 0x1000
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0x41000000 0x10000
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0x42000000 0x100000>;
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bus-range = <0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
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0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
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0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
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interrupt-map-mask = <0x1800 0 0 7>;
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interrupt-map = <0x1800 0 0 1 &sic 28
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0x1800 0 0 2 &sic 29
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0x1800 0 0 3 &sic 30
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0x1800 0 0 4 &sic 27
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0x1000 0 0 1 &sic 27
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0x1000 0 0 2 &sic 28
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0x1000 0 0 3 &sic 29
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0x1000 0 0 4 &sic 30
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0x0800 0 0 1 &sic 30
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0x0800 0 0 2 &sic 27
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0x0800 0 0 3 &sic 28
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0x0800 0 0 4 &sic 29
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0x0000 0 0 1 &sic 29
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0x0000 0 0 2 &sic 30
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0x0000 0 0 3 &sic 27
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0x0000 0 0 4 &sic 28>;
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};
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fpga {
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mmc@5000 {
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/*
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* Overrides the interrupt assignment from
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* the Versatile AB board file.
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*/
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interrupts-extended = <&sic 22 &sic 23>;
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};
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uart@9000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x9000 0x1000>;
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interrupt-parent = <&sic>;
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interrupts = <6>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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sci@a000 {
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compatible = "arm,primecell";
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reg = <0xa000 0x1000>;
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interrupt-parent = <&sic>;
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interrupts = <5>;
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clocks = <&xtal24mhz>;
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clock-names = "apb_pclk";
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};
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mmc@b000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0xb000 0x1000>;
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interrupt-parent = <&sic>;
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interrupts = <1>, <2>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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};
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};
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};
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};
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